FPGA Design for PCANet Deep Learning Network

Zhou, Yuteng; Wang, Wei; Huang, Xinming

doi:10.1109/fccm.2015.45

Cited by 7 publications

(2 citation statements)

References 3 publications

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“…Such design would be a fine-grained architecture. However, such architecture is unpractical due to the very high hardware requirements in occupation and interconnection lines, which leads to high power and high resource usage, along with low speed architectures [16]. A different approach might use neuron units with serial processing, which is more practical because every unit just requires one Multiply-And-Accumulate (MAC) block, time-multiplexing data into the same units [17].…”

Section: Introductionmentioning

confidence: 99%

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

et al. 2019

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New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in layers, and a number of layers. The hardware combines matrix algebra concepts with serial-parallel computation. It is based on a systolic ring of neural processing elements (NPE), only requiring as many NPEs as neuron units in the largest layer, no matter the number of layers. The use of resources grows linearly with the number of NPEs. This versatile architecture serves as an accelerator in real-time applications and its size does not affect the system clock frequency. Unlike most approaches, a single activation function block (AFB) for the whole FFNN is required. Performance, resource usage, and accuracy for several network topologies and activation functions are evaluated. The architecture reaches 550 MHz clock speed in a Virtex7 FPGA. The proposed implementation uses 18-bit fixed point achieving similar classification performance to a floating point approach. A reduced weight bit size does not affect the accuracy, allowing more weights in the same memory. Different FFNN for Iris and MNIST datasets were evaluated and, for a real-time application of abnormal cardiac detection, a ×256 acceleration was achieved. The proposed architecture can perform up to 1980 Giga operations per second (GOPS), implementing the multilayer FFNN of up to 3600 neurons per layer in a single chip. The architecture can be extended to bigger capacity devices or multi-chip by the simple NPE ring extension.INDEX TERMS Feedforward neural networks -FFNN, systolic hardware architecture, FPGA implementation, neural network acceleration, deep neural networks.

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Section: Introductionmentioning

confidence: 99%

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks

et al. 2019

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“…For example, Lei [10] obtained good face recognition by concatenating PCANet's first-and second-stage image codes into a higher-dimensional feature by arranging them in a stack. Zhou [11] implemented the PCANet framework with field programmable gate array hardware. Zheng [12] applied PCANet to age estimation tasks to implement an efficient age estimation system.…”

Section: Introductionmentioning

confidence: 99%

ICANet: a simple cascade linear convolution network for face recognition

Zhang

Geng

et al. 2018

J Image Video Proc.

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Recently, deep convolutional networks have demonstrated their capability of improving the discriminative power compared with other machine learning method, but its feature learning mechanism is not very clear. In this paper, we present a cascaded linear convolutional network, based on independent component analysis (ICA) filters, named ICANet. ICANet consists of three parts: a convolutional layer, a binary hash, and a block histogram. It has the following advantages over other methods: (1) the network structure is simple and computationally efficient, (2) the ICA filter is trained with an unsupervised algorithm using unlabeled samples, which is practical, and (3) compared to deep learning models, each layer parameter in ICANet can be easily trained. Thus, ICANet can be used as a benchmark for the application of a deep learning framework for large-scale image classification. Finally, we test two public databases, AR and FERET, showing that ICANet performs well in facial recognition tasks.

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