FPGA Design of SAR Type ADC Based Analog Input Module for Industrial Applications

Dhanabalan, G.; Murugan, T.

doi:10.1007/978-981-15-6229-7_8

Cited by 2 publications

(4 citation statements)

References 16 publications

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“…The working principle of successive approximation register (S is preferred in many applications, as mentioned in [24] This work has proposed a novel conversion process of analog signa which can be seen in Figure 3. It was developed, simulated, and verified u [25]. This work has proposed a novel conversion process of analog signals into digital, which can be seen in Figure 3.…”

Section: Single Closed-loop Control System-proposedmentioning

confidence: 99%

“…This work has proposed a novel conversion process of analog signals into digital, which can be seen in Figure 3. It was developed, simulated, and verified using Multisim [25]. This work has proposed a novel conversion process of analog signals into digital, which can be seen in Figure 3.…”

Section: Single Closed-loop Control System-proposedmentioning

confidence: 99%

“…This work has proposed a novel conversion process of analog signals into digital, which can be seen in Figure 3. It was developed, simulated, and verified using Multisim [25]. It functions on the working principle of successive approximation register (SAR) type ADC.…”

Section: Single Closed-loop Control System-proposedmentioning

confidence: 99%

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Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Dhanabalan¹,

Selvi²,

Mahdal

2022

Sensors

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A programmable logic controller (PLC) executes a ladder diagram (LD) using input and output modules. An LD also has PID controller function blocks. It contains as many PID function blocks as the number of process parameters to be controlled. Adding more process parameters slows down PLC scan time. Process parameters are measured as analog signals. The analog input module in the PLC converts these analog signals into digital signals and forwards them to the PID controller as inputs. In this research work, a field-programmable gate array (FPGA)-based multiple PID controller is proposed to retain PLC scan time at a lower value. Concurrent execution of multiple PID controllers was assured by assigning separate FPGA hardware resources for every PID controller. Digital input to the PID controller is routed by the novel idea of analog to digital conversion (ADC), performed using a digital to analog converter (DAC), comparator, and FPGA. ADC combined with dedicated PID controller logic in an FPGA for every closed-loop control system confirms concurrent execution of multiple PID controllers. The time required to execute two closed-loop controls was identified as 18.96000004 ms. This design can be used either with or without a PLC.

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Section: Single Closed-loop Control System-proposedmentioning

confidence: 99%

Section: Single Closed-loop Control System-proposedmentioning

confidence: 99%

See 1 more Smart Citation

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Dhanabalan¹,

Selvi²,

Mahdal

2022

Sensors

View full text Add to dashboard Cite

show abstract

“…Most AD converter applications can be classified into five general segments. The first segment is data acquisition [1,2], the second segment includes audio and voice applications [3,4], and the third segment includes industrial measurements [5][6][7]. Subsequently, there is control or feedback digital control, and the last segment involves very fast applications such as high-frequency devices [8,9], video processing [10], etc.…”

Section: Introductionmentioning

confidence: 99%

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors

Sokol,

Galajda,

Saliga

et al. 2024

Sensors

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The article presents the analysis, design, and low-cost implementation of application-specific AD converters for M-sequence-based UWB applications to minimize and integrate the whole UWB sensor system. Therefore, the main goal of this article is to integrate the AD converter’s own design with the UWB analog part into the system-in-package (SiP) or directly into the system-on-a-chip (SoC), which cannot be implemented with commercial AD converters, or which would be disproportionately expensive. Based on the current and used UWB sensor system requirements, to achieve the maximum possible bandwidth in the proposed semiconductor technology, a parallel converter structure is designed and presented in this article. Moreover, 5-bit and 4-bit parallel flash AD converters were initially designed as part of the research and design of UWB M-sequence radar systems for specific applications, and are briefly introduced in this article. The requirements of the newly proposed specific UWB M-sequence systems were established based on the knowledge gained from these initial designs. After thorough testing and evaluation of the concept of the early proposed AD converters for these specific UWB M-sequence systems, the design of a new AD converter was initiated. After confirming sufficient characteristics based on the requirements of UWB M-sequence systems for specific applications, a 7-bit AD converter in low-cost 0.35 µm SiGe BiCMOS technology from AMS was designed, fabricated, and presented in this article. The proposed 7-bit AD converter achieves the following parameters: ENOB = 6.4 bits, SINAD = 38 dB, SFDR = 42 dBc, INL = ±2-bit LSB, and DNL = ±1.5 LSB. The maximum sampling rate reaches 1.4 Gs/s, the power consumption at 20 Ms/s is 1050 mW, and at 1.4 Gs/s is 1290 mW, with a power supply of −3.3 V.

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FPGA Design of SAR Type ADC Based Analog Input Module for Industrial Applications

Cited by 2 publications

References 16 publications

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Scan Time Reduction of PLCs by Dedicated Parallel-Execution Multiple PID Controllers Using an FPGA

Design of AD Converters in 0.35 µm SiGe BiCMOS Technology for Ultra-Wideband M-Sequence Radar Sensors

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