FPGA HLS Today: Successes, Challenges, and Opportunities

Cong, Jason; Lau, Jason; Liu, Gai; Neuendorffer, Stephen; Pan, Peichen; Vissers, Kees; Zhang, Zhiru

doi:10.1145/3530775

Cited by 79 publications

(15 citation statements)

References 91 publications

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“…For example, when designing with HLS, each component can be simulated at the RTL level using the C models of the other components, and can easily take advantage of both coarse-grained and fine-grained parallelism. This allows designers to focus more on the high-level algorithm and architecture design without worrying about low-level implementation details ( Cong et al, 2022 ).…”

Section: Discussionmentioning

confidence: 99%

A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities

Yao

Tang

et al. 2022

PeerJ Computer Science

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Graph convolutional networks (GCNs) based on convolutional operations have been developed recently to extract high-level representations from graph data. They have shown advantages in many critical applications, such as recommendation system, natural language processing, and prediction of chemical reactivity. The problem for the GCN is that its target applications generally pose stringent constraints on latency and energy efficiency. Several studies have demonstrated that field programmable gate array (FPGA)-based GCNs accelerators, which balance high performance and low power consumption, can continue to achieve orders-of-magnitude improvements in the inference of GCNs models. However, there still are many challenges in customizing FPGA-based accelerators for GCNs. It is necessary to sort out the current solutions to these challenges for further research. For this purpose, we first summarize the four challenges in FPGA-based GCNs accelerators. Then we introduce the process of the typical GNN algorithm and several examples of representative GCNs. Next, we review the FPGA-based GCNs accelerators in recent years and introduce their design details according to different challenges. Moreover, we compare the key metrics of these accelerators, including resource utilization, performance, and power consumption. Finally, we anticipate the future challenges and directions for FPGA-based GCNs accelerators: algorithm and hardware co-design, efficient task scheduling, higher generality, and faster development.

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Section: Discussionmentioning

confidence: 99%

A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities

Yao

Tang

et al. 2022

PeerJ Computer Science

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“…One approach, called High-Level Synthesis (HLS), uses SW-oriented computation models, with languages like SystemC (5) or directly C. With this approach, the simulation consists simply in executing the compiled SW code. It has the advantages of simplicity and fast simulation but suffers from a lack of accuracy leading to inconsistencies with lower-level representations (6) . Another approach uses languages with simplified models of computation, like synchronous computing for the PARTHENON (7) CAD.…”

Section: Related Workmentioning

confidence: 99%

Implementation and Comparison of Several Register Transfer Level Simulation Engines for the HDLRuby Language

Gauthier

Ishikawa

2023

The Proceedings of the 11th IIAE International Conference on Industrial Application Engineering 2023

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HDLRuby is a new hardware description language (HDL) based on Ruby that focuses on design productivity. This language is already mature enough to design complex circuits but it still requires a fast simulator to become a realistic alternative to de-facto standards like VHDL or Verilog HDL. In this paper, we present and compare four implementation strategies for simulating hardware descriptions in HDLRuby. The first strategy consists in generating Verilog HDL and using a state-of-the-art simulator for this language, the second one generates the C code of a standalone simulator, the third one directly executes the internal representation (IR) of HDLRuby using the Ruby interpreter, and the fourth one integrates compiled C with Ruby for fast interpretation of the HDLRuby IR. Experimental results show that the last approach is on average the fastest, and does not have any case of plummeting performance contrary to the other strategies.

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“…High-Level Synthesis (HLS) technology is now mature to address large applications both on Field Programmable Gate-Array (FPGA) and Application-Specific Integrated Circuit (ASIC), with industrial tools Xilinx Vitis HLS and Intel HLS for FPGA, Catapult from Siemens and Stratus HLS from Cadence for ASIC, and open-source tools LegUp and Bambu [12]. Those tools have been proved efficient to create statically scheduled kernels based on sequential algorithms described in C/C++.…”

Section: Introductionmentioning

confidence: 99%

Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow

Honorat,

Dardaillon,

Miomandre

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

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High-Level Synthesis (HLS) tools are mature enough to provide efficient code generation for computation kernels on FPGA hardware. For more complex applications, multiple kernels may be connected by a dataflow graph. Although some tools, such as Xilinx Vitis HLS, support dataflow directives, they lack efficient analysis methods to compute the buffer sizes between kernels in a dataflow graph. This paper proposes an original method to safely approximate such buffer sizes. The first contribution computes an initial overestimation of buffer sizes, wihout knowing the memory access patterns of kernels. The second contribution iteratively refines those buffer sizes thanks to cosimulation. Moreover, the paper introduces an open source framework using these methods to facilitate dataflow programming on FPGA using HLS. The proposed methods and framework have been tested on 7 dataflow applications, and outperform Vitis HLS cosimulation in 5 benchmarks, either in terms of BRAM and LUT usage, or in term of exploration time. In the 2 other benchmarks, our best method gets results similar to Vitis HLS. Last but not least, our method admits directed cycles in the application graphs.

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FPGA HLS Today: Successes, Challenges, and Opportunities

Cited by 79 publications

References 91 publications

A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities

A survey of field programmable gate array (FPGA)-based graph convolutional neural network accelerators: challenges and opportunities

Implementation and Comparison of Several Register Transfer Level Simulation Engines for the HDLRuby Language

Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow

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