FPGA Implementation of 32 Bit Complex Floating Point Multiplier Using Vedic Real Multipliers with Minimum Path Delay

Rao, K. Deergha; Muralikrishna, P.; Gangadhar, Ch.

doi:10.1109/upcon.2018.8597031

Cited by 11 publications

(3 citation statements)

References 2 publications

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“…Again, in the same year, Anil Kumar Gupta designed multiplier by using 180nm cadence EDA tool and simulated using specter simulator. These papers describe the propose of 8-bit multiplier architecture [21].…”

Section: Literature Reviewmentioning

confidence: 99%

Analysis of Multiplication Based on Vedic Mathematics

Lakshmi

Kishore

Kumar

2022

Advances in Transdisciplinary Engineering

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The usual segmentation methods were addressed here: edge detection, clustering, and region growth. The problem with segmentation is that no one approach is suited for a certain type of picture, nor are all techniques applicable to all images. The importance of multiplication is rising according to the technology process. It is one of the major applications which is used in various domains such as business and digital signal process etc. The way of general multiplication is much more time taking process. So, mainly as to remove this time delay in this paper the concept of Vedic mathematics is introduced. This paper introduced about Indian ancient Vedic mathematics is involved to clear those problems. Sixteen sutras among the Vedic mathematics the one sutra that is widely used and implemented is “URDHVA-TIRYAGBHYAM” is proposed. The multiplication process of two 4 bit and two 3 bit and also two 2-bit multiplications are gone through this paper. This process ultimately leads to the consumption of less time and faster implementation. But, with respect to the order of multiplication, the complexity will also increase. When compared to other multipliers it takes less area.

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Section: Literature Reviewmentioning

confidence: 99%

Analysis of Multiplication Based on Vedic Mathematics

Lakshmi

Kishore

Kumar

2022

Advances in Transdisciplinary Engineering

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“…In 32-bit complex floating point (FP) multiplier utilizing 4 FP real multipliers with less path delay [9]. The whole 32-bit real FP multiplier requires a 24-bit fixed point real multiplier for mantissa multiplication.…”

Section: Table1: Comparison Of Mantissa Multipliermentioning

confidence: 99%

Merged Floating Point Multipliers

2019

IJEAT

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Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recognized i.e, resource sharing Karatsuba –Ofman algorithm which occupies less area, power and increasing speed. The design was implemented in mat lab using DSP block sets, simulator tool is Xilinx Vivado.

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“…There are two types of storage layouts in IEEE floating point 754, namely single (32 bit) and double (64 bit) [9] [10]. Table 1 presents the IEEE floating point 754 32 bit and 64 bit standard components [11] [12].…”

Section: Introductionmentioning

confidence: 99%

Integer Representation of Floating-Point Manipulation with Float Twice

Kurniawan

Ardiansyah

Oktavianita

et al. 2020

IJID

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In the programming world, understanding floating point is not easy, especially if there are floating point and bit-level interactions. Although there are currently many libraries to simplify the computation process, still many programmers today who do not really understand how the floating point manipulation process. Therefore, this paper aims to provide insight into how to manipulate IEEE-754 32-bit floating point with different representation of results, which are integers and code rules of float twice. The method used is a literature review, adopting a float-twice prototype using C programming. The results of this study are applications that can be used to represent integers of floating-point manipulation by adopting a float-twice prototype. Using the application programmers make it easy for programmers to determine the type of program data to be developed, especially those running on 32 bits floating point (Single Precision).

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FPGA Implementation of 32 Bit Complex Floating Point Multiplier Using Vedic Real Multipliers with Minimum Path Delay

Cited by 11 publications

References 2 publications

Analysis of Multiplication Based on Vedic Mathematics

Analysis of Multiplication Based on Vedic Mathematics

Merged Floating Point Multipliers

Integer Representation of Floating-Point Manipulation with Float Twice

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