FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier

Baesler, Malte; Teufel, Thomas

doi:10.1109/reconfig.2009.17

Cited by 10 publications

(9 citation statements)

References 6 publications

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“…The accurate MAC unit can be clocked with up to 100 MHz. Compared to a previously published paper [10], this is an improvement by a factor of five. In comparison, a software implementation of a single 16 digits floating-point multiplication without any long accumulator on a highperformance processor already uses 233 cycles, on lower performance architectures even more [27].…”

Section: Synthesis Resultsmentioning

confidence: 55%

“…Contrary to this, in the new FPGA-based design presented here, we use a fast parallel decimal multiplier and a parallel accurate scalar product unit that can be pipelined to improve latency. This paper summarizes and extends the research published in [10]; in particular, it gives a more detailed introduction and description of the proposed architecture. Furthermore, we improved the speed of the decimal fixedpoint multiplier by a factor of two and the accurate scalar product unit by a factor of five, respectively.…”

Section: Introductionmentioning

confidence: 64%

“…Contrary to the several works on implementations in ASICs, decimal multipliers are not often implemented in FPGAs. These few are [10,18,21]. The method in [21] exploits the FPGA's internal binary adders and uses decimal to binary conversion and vice versa.…”

Section: Decimal Fixed-point Multipliermentioning

confidence: 99%

“…The decimal multiplication in [18] is sequentially and is based on digit-by-digit multipliers that are implemented by memory (BRAM or distributed RAM). It also describes a combinational multiplier design which is only applicable for small precisions p. In a recent work [10], we proposed a fully combinational decimal fixedpoint multiplier optimized for Xilinx Virtex-II Proarchitectures [22]. It is based on fast partial product generation and a combinational fast carry save adder tree.…”

Section: Decimal Fixed-point Multipliermentioning

confidence: 99%

“…To prevent timeconsuming ripple-carry propagations due to sign swapping and overflow, we use a so-called carry cache (CC) that buffers any overflow signals. Contrary to a previously published paper [10], in this work, we have simplified the carry handling by removing the principle of fast carry resolution in case of a carry cache overflow. Instead, we have increased the block size of the long accumulator for carry cache (LACC) to 16 digits, assuming that the CC will never overflow.…”

Section: Proposed Accurate Scalar Product Unitmentioning

confidence: 99%

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A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA

Baesler

Voigt

Teufel

2010

International Journal of Reconfigurable Computing

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Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, we present a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipeline stages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unit for IEEE 754-2008decimal64data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unit and migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accurate scalar product unit's latency even by a factor of five.

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Section: Synthesis Resultsmentioning

confidence: 55%

Section: Introductionmentioning

confidence: 64%

Section: Decimal Fixed-point Multipliermentioning

confidence: 99%

Section: Decimal Fixed-point Multipliermentioning

confidence: 99%

Section: Proposed Accurate Scalar Product Unitmentioning

confidence: 99%

See 3 more Smart Citations

A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA

Baesler

Voigt

Teufel

2010

International Journal of Reconfigurable Computing

Self Cite

View full text Add to dashboard Cite

show abstract

Taxonomy of Decimal Multiplier Research

Sengupta

Sultana

2018

Algorithms and Applications

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On high-performance parallel decimal fixed-point multiplier designs

Zhu

Jiang

Yang

et al. 2014

Computers & Electrical Engineering

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a b s t r a c tHigh-performance, area and power efficient hardware implementation of decimal multiplication is preferred to slow software simulations in various key scientific and financial applications, where errors caused by converting decimal numbers into their approximate binary representations are unacceptable. This paper presents a parallel architecture for fixed-point 8421-BCD-based decimal multiplication. In essence, it applies a hybrid 8421-5421 recoding scheme to generate partial products, and accumulates them with 8421 carry-lookahead adders organized as a tree structure. In addition, we propose a 4221-BCD-based decimal multiplier that is built upon a novel 4221-BCD full adder; operands of this 4221 multiplier are directly represented in the 4221 BCD. The proposed 16 Â 16 decimal multipliers are compared with other best-known decimal multiplier designs with a TSMC 90-nm technology, and the evaluation results show that the proposed 8421-5421 multiplier achieves the lowest delay and area, as well as the highest power efficiency, among all the existing hardware-based BCD multipliers.

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FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier

Cited by 10 publications

References 6 publications

A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA

A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA

Taxonomy of Decimal Multiplier Research

On high-performance parallel decimal fixed-point multiplier designs

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