FPGA implementation of a Deep Belief Network architecture for character recognition using stochastic computation

Sanni, Kayode; Garreau, Guillaume; Molin, Jamal Lottier; Andreou, Andreas G.

doi:10.1109/ciss.2015.7086904

Cited by 39 publications

(10 citation statements)

References 19 publications

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“…12, the ISI max value for N = 64 is 0.5 of the ISI max value for N = 32 and so on. The experimental result follows the trend in (13) that N ISI max is a constant.…”

Section: A Accumulation Of Hazardsupporting

confidence: 73%

“…This stochastic spiking network can also be trained on-line by using an event-driven approach of the training method for the RBM [11]. A spiking RBM has been mapped on the neuromorphic TrueNorth system with digital spiking neurons and by using a noisy threshold model to implement the Gibbs sampler [12] and a spiking DBN was implemented on the FPGA using inputs encoded as unary streams [13].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Hardware Implementation of an Event-Based Message Passing Graphical Model Network

Chien

Longinotti

Steimer

et al. 2018

IEEE Trans. Circuits Syst. I

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This paper presents a hardware system that implements a factor graph, where messages are sent using an event-based belief propagation algorithm. The system, comprising an FPGA and an application specific integrated circuit (ASIC) chip, can be used to construct a graph with upto 16 output message channels. The ASIC chip with 16 channels is fabricated in a 0.35 um 2P4M CMOS process and occupies 2.16 × 2.74 mm 2 . Each channel dissipates 46 uW. The output analog messages of the channels are encoded through the interspike intervals of the output spike streams or events. The system can be used to implement graphs with arbitrary variable distributions for its inputs and using constraint functions, such as "plus" and "equality". Using Kullback-Leibler divergence, we show that the measured distributions from the implemented graphs on the hardware show close similarity to the theoretical distributions.

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“…12, the ISI max value for N = 64 is 0.5 of the ISI max value for N = 32 and so on. The experimental result follows the trend in (13) that N ISI max is a constant.…”

Section: A Accumulation Of Hazardsupporting

confidence: 73%

Section: Introductionmentioning

confidence: 99%

Hardware Implementation of an Event-Based Message Passing Graphical Model Network

Chien

Longinotti

Steimer

et al. 2018

IEEE Trans. Circuits Syst. I

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show abstract

“…In recent years, different hardware architectures have been presented for the character recognition task. In [ 66 ], Sanni et al presented a hardware implementation of a deep belief network architecture for character recognition using stochastic computation. The authors evaluated their architecture on a Kintex-7 FPGA device for the MNIST database of handwritten digits [ 67 ].…”

Section: Related Workmentioning

confidence: 99%

iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

et al. 2021

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In recent years, there has been an increasing demand to digitize and electronically access historical records. Optical character recognition (OCR) is typically applied to scanned historical archives to transcribe them from document images into machine-readable texts. Many libraries offer special stationary equipment for scanning historical documents. However, to digitize these records without removing them from where they are archived, portable devices that combine scanning and OCR capabilities are required. An existing end-to-end OCR software called anyOCR achieves high recognition accuracy for historical documents. However, it is unsuitable for portable devices, as it exhibits high computational complexity resulting in long runtime and high power consumption. Therefore, we have designed and implemented a configurable hardware-software programmable SoC called iDocChip that makes use of anyOCR techniques to achieve high accuracy. As a low-power and energy-efficient system with real-time capabilities, the iDocChip delivers the required portability. In this paper, we present the hybrid CPU-FPGA architecture of iDocChip along with the optimized software implementations of the anyOCR. We demonstrate our results on multiple platforms with respect to runtime and power consumption. The iDocChip system outperforms the existing anyOCR by 44× while achieving 2201× higher energy efficiency and a 3.8% increase in recognition accuracy.

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“…It has the ability of self-learning and self-adaptation. Neural networks include feed-forward neural networks [5], BP neural networks [6], deep belief networks, and convolutional neural networks [7]. Among them, CNN not only has the traditional neural network's strong fault tolerance, self-learning, and adaptive ability but also has the characteristics of automatic extraction characteristics, local connections, and weight sharing.…”

Section: Hand-written Word Recognition Research Status Quomentioning

confidence: 99%

The Study of Handwriting Recognition Algorithms Based on Neural Networks

Finkelstein¹,

Kuncan²

2021

IJHIT

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Handwriting Identifies basic graph-like problems and has a high real-world value in areas such as cloud accounting, finance, and postal administration. Due to the unrestricted problem of handwritten numbers when writing, it is relatively difficult to achieve rapid and effective recognition. With the emergence of deep learning-related algorithms and the rapid development of computer hardware technology, image classification methods based on Convolutional Neural Network (CNN) have gradually become a research hotspot. Because the convolutional network has a strong letter numbering ability and network generalization ability, the recognition rate can often exceed the traditional graph classing method. Therefore, the study of hand-written word recognition should be implemented using CNN through the network. Handwriting Word Recognition is the key technique for self-identification. Therefore, summarizing and analyzing the existing handwritten digit recognition algorithms, two handwritten digit recognition algorithms based on Convolutional Neural Network (CNN) are proposed. To improve the recognition performance of the CNN model, this article proposes a handwriting recognition algorithm based on the change to CNN. To extract the image feature information more fully, this paper proposes a handwriting recognition algorithm based on feature fusion and SVM. First, using the modified CNN model and the Gabor filter that introduces curvature systems, extract the CNN and Gabor characteristics of the character image; Second, the characteristics of its progress are fused to obtain more effective new features; Finally, the fusion feature is entered into the SVM classifier into the line number of words to recognize. The results of the experiment show that the algorithm can effectively improve the recognition effect of handwritten words

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FPGA implementation of a Deep Belief Network architecture for character recognition using stochastic computation

Cited by 39 publications

References 19 publications

Hardware Implementation of an Event-Based Message Passing Graphical Model Network

Hardware Implementation of an Event-Based Message Passing Graphical Model Network

iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing

The Study of Handwriting Recognition Algorithms Based on Neural Networks

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