FPGA implementation of a General Regression Neural Network: An embedded pattern classification system

Polat, Övünç; Yıldırım, Tülay

doi:10.1016/j.dsp.2009.10.013

Cited by 35 publications

(17 citation statements)

References 7 publications

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“…It can be seen that the FPGA chip is sufficient to perform the whole pulse mode RBFNN architecture, thus a larger network can be realized without sacrificing its response time, which enable to perform real time applications. Comparisons with conventional techniques and Neural ones [5,12], reveals the compactness of the suggested hybrid on-chip learning design and its ability to reduce the hardware resource costs. …”

Section: Simulation Results and Synthesismentioning

confidence: 99%

“…Hardware implementation is accordingly devoted to the generalization phase using the network parameters set. However, the speed of software-based implementation is low, and it is not suitable for using in some environments where high performance is needed [5]. Size and real-time operations show that on-chip learning is necessary for a large range of applications.…”

Section: Introductionmentioning

confidence: 99%

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Digital Hardware Pulse-Mode RBFNN with Hybrid On-chip Learning Algorithm Based Edge Detection.

Gargouri

Masmoudi²

2012

Journal of Advanced Computer Science &Amp; Technology

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A hardware implementation of pulse mode Radial Basis Function Neural Network (RBFNN) with on-chip learning ability is proposed in this paper. Pulse mode presents an emerging technology in digital implementation of neural networks thanks to its higher density of integration. However, hardware on-chip learning is a difficult issue, since the back-propagation algorithm is the most used, which requires a large number of logic gates in the hardware. To overcome this problem, we apply a hybrid process, which is split into two stages. In the first one, the K-means algorithm is used to update the centers of gaussian activation functions. Thereafter, the connection weights are adjusted using the back-propagation algorithm. Details of important aspects concerning the hardware implementation are given. As illustration of the efficiency and scalability of the proposed design, we consider edge detection operation which is a very important step in image processing. In the learning step, the RBFNN was taught the Canny operator behavior. Experiential results show good approximation features. The proposed design was implemented on a virtex II PRO FPGA platform and synthesis results showed higher performances when benchmarked against conventional techniques and neural ones.

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Section: Simulation Results and Synthesismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Digital Hardware Pulse-Mode RBFNN with Hybrid On-chip Learning Algorithm Based Edge Detection.

Gargouri

Masmoudi²

2012

Journal of Advanced Computer Science &Amp; Technology

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“…The execution time and hardware space used is excessively better on FPGA [7,9,10,13] when comparing the classical electronic chips. FPGA chips have endless reconfigurations advantages according to ASIC's, CPLD's or DSP's.…”

Section: Resultsmentioning

confidence: 99%

“…The first comparison item is implementation area. The proposed FPGA-based intelligent hardware implementation [7,[10][11][12][13] is very suitable method for the semiconductor circuit elements.…”

Section: Resultsmentioning

confidence: 99%

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The Modeling and Hardware Implementation of Semiconductor Circuit Elements by Using ANN and FPGA

Tuntaş

2015

Acta Phys. Pol. A

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This study, the modeling and hardware implementation of semiconductor circuit elements very frequently used in electronic circuits are carried out by using artificial neural networks and field programmable gate array chip. Initially the artificial neural network models obtained has been written in very high speed integrated circuit hardware description language (VHDL). Then, these configurations have been simulated and tested under ModelSim Xilinx software. Finally, the best configuration has been implemented under the Xilinx Spartan-3E FPGA (XC3S500E) chip of Xilinx. The modeling of electronic circuit elements is very important both in respect of engineering, and in respect of practical mathematics. The main aim is to shorten the simulation time and to examine the real physical system applications easily by using the model elements instead of using the ones used in real applications. The effectiveness of the implemented artificial neural network models on field programmable gate array was found successful.

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Decoding the nonstationary neural activity in motor cortex for brain machine interfaces

Zhang

Liao

Zheng

et al. 2011

Int J Imaging Syst Tech

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Previous decoding algorithms used in brain machine interfaces (BMIs) usually seek a static functional mapping between the spatio-temporal neural activity and behavior and assume that the neural spike statistics do not change over time. However, recent work indicates the significant variance in neural activities, which suggests the nonfeasibility of the stationary assumptions on the neural signal sequences. To track the time-changing neural activity during the nonlinear decoding process, we developed a time-varying approach based on general regression neural network (GRNN) with a dynamic pattern layer. Applied on both simulated neural activity and in vivo BMI data extracted from rat's motor cortex, the proposed method reconstructs the movement signals better than the original GRNN algorithm with static pattern layer, which raises the promise of successfully tracking the time-varying neural activity for BMIs decoding. V

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FPGA implementation of a General Regression Neural Network: An embedded pattern classification system

Cited by 35 publications

References 7 publications

Digital Hardware Pulse-Mode RBFNN with Hybrid On-chip Learning Algorithm Based Edge Detection.

Digital Hardware Pulse-Mode RBFNN with Hybrid On-chip Learning Algorithm Based Edge Detection.

The Modeling and Hardware Implementation of Semiconductor Circuit Elements by Using ANN and FPGA

Decoding the nonstationary neural activity in motor cortex for brain machine interfaces

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