FPGA Implementation of an Adaptive Noise Canceller

Abstract

This paper proposes an FPGA implementation of anAdaptive Noise Canceller using the Least Mean Square (LMS) algorithm. The hardware architecture is synthesized using the Xilinx Spartan-3e Starter Kit as the target board. The experimental result of the hardware implementation shows the performance of LMS algorithm under different conditions and the feasibility of our architecture. A comparison between hardware and pure software implementation is then made with different filter taps.

An Overview of Reconfigurable Hardware for Efficient Implementation of DSP Algorithms

“…There are various noise canceller deputed in literature, Adaptive noise canceller using LMS algorithm mapped to FPGA presented in [16]. In this paper comparison between hardware and software implementation is made for different filter taps.…”

Fpga Implementation of Optimal Step Size NLMS Algorithm and Its Performance Analysis

“…However, there are several issues that need to be addressed [4][5]. When performing software simulation of adaptive filters, calculations are normally carried out with floating point precision.…”