FPGA Implementation of Buffer-Less NoC Router for SDM-Based Network-on-Chip

Babu, Y. Amar; Prasad, G. M. V.; Solomon, John Bedford

doi:10.1007/978-981-10-6875-1_55

Cited by 1 publication

(1 citation statement)

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“…A Nirgam simulator is used to evaluate the suggested algorithm whose capabilities are listed in Table 2 [ 13 , 19 ]. The main components in this simulator are routers, processing elements, links, and buffers [ 43 , 44 ]. Moreover, the configuration parameters for the analysis and simulation of the suggested method are given in Table 3 .…”

Section: Experiments and Simulation Environmentmentioning

confidence: 99%

Providing an Adaptive Routing along with a Hybrid Selection Strategy to Increase Efficiency in NoC‐Based Neuromorphic Systems

Trik

Mozaffari

Bidgoli

2021

Computational Intelligence and Neuroscience

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Effective and efficient routing is one of the most important parts of routing in NoC-based neuromorphic systems. In fact, this communication structure connects different units through the packets routed by routers and switches embedded in the network on a chip. With the help of this capability, not only high scalability and high development can be created, but by decreasing the global wiring to the chip level, power consumption can be reduced. In this paper, an adaptive routing algorithm for NoC-based neuromorphic systems is proposed along with a hybrid selection strategy. Accordingly, a traffic analyzer is first used to determine the type of local or nonlocal traffic depending on the number of hops. Then, considering the type of traffic, the RCA and NoP selection strategies are used for the nonlocal and local strategies, respectively. Finally, using the experiments that performed in the simulator environment, it has been shown that this solution can well reduce the average delay time and power consumption.

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