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The design of new electronic systems is getting more complex as more functionality is integrated into these systems. To design complex system, a predictable design flow is needed. A soft processor based System-on-Chip (SoC) is often mentioned as the hardware platform to be used in modern electronics systems for fast prototyping on FPGA. In this paper, a novel area and power efficient on chip communication architectures has been proposed for image encryption and decryption using single soft processor(Micro Blaze). Proposed System On Chip explores On chip Communication architectures features to efficiently implement the application. The SoC offers scalability and guarantees on the timing behavior when communicating data between various processing and storage elements. Proposed SoC has been implemented on Spartan6 FPGA and evaluated at 83.33MHz. It has occupied only 19% of resources available on target FPGA , consumes very low power. The proposed on chip communication architectures compared with device utilization on FPGA and power consumed.

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To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability, system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.