FPGA Implementation of Decision Trees and Tree Ensembles for Character Recognition in Vivado Hls

Kułaga, Rafał; Gorgon, Marek Boguslaw

doi:10.1515/ipc-2015-0012

Cited by 27 publications

(15 citation statements)

References 14 publications

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“…However they do not support GBDT and they apply their techniques only to simple case studies. Reference [15] proposes to use a high-level synthesis approach to design an FPGA accelerator. They focus on Random Forest, which is an ensemble technique that calculates the average value of several trees trained with different input data to generate a more accurate and robust final output.…”

Section: Related Workmentioning

confidence: 99%

FPGA Accelerator for Gradient Boosting Decision Trees

Alcolea

Resano

2021

Electronics

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A decision tree is a well-known machine learning technique. Recently their popularity has increased due to the powerful Gradient Boosting ensemble method that allows to gradually increasing accuracy at the cost of executing a large number of decision trees. In this paper we present an accelerator designed to optimize the execution of these trees while reducing the energy consumption. We have implemented it in an FPGA for embedded systems, and we have tested it with a relevant case-study: pixel classification of hyperspectral images. In our experiments with different images our accelerator can process the hyperspectral images at the same speed at which they are generated by the hyperspectral sensors. Compared to a high-performance processor running optimized software, on average our design is twice as fast and consumes 72 times less energy. Compared to an embedded processor, it is 30 times faster and consumes 23 times less energy.

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Section: Related Workmentioning

confidence: 99%

FPGA Accelerator for Gradient Boosting Decision Trees

Alcolea

Resano

2021

Electronics

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“…Kulaga et al [24] have proposed FPGA implementation of decision tree and its ensemble for letter and digit recognisition using Vivado High Level Synthesis tool. It is explained about Vivado HLS that it is one of the tool available for Xilinx FPGAs and Zynq SoC devices for synthesisation.…”

Section: Literature Surveymentioning

confidence: 99%

Implementation of decision tree algorithm on FPGA devices

Malhotra

Singh

2021

IJ-AI

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<span id="docs-internal-guid-01e673b1-7fff-8dc3-6b99-14ed17cd6b49"><span>Machine learning techniques are rapidly emerging in large number of fields from robotics to computer vision to finance and biology. One important step of machine learning is classification which is the process of finding out to which category a new encountered observation belongs based on predefined categories. There are various existing solutions to classification and one of them is decision tree classification (DTC) which can achieve high accuracy while handling the large datasets. But DTC is computationally intensive algorithm and as the size of the dataset increases its running time also increases which could be from some hours to days even. But thanks to field programmable gate arrays (FPGA) which could be used for large datasets to achieve high performance implementation with low energy consumption. Along with FPGA’s, python is used for accelerating the application development and python is leveraged by using python productivity for zynq (PYNQ), a python development environment for application development. This paper provides the literature review of an implementation of DTC for FPGA devices along with future work that can be done.</span></span>

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“…However, the paper reported that the proposed implementation can reduce the consumed energy by 93.7% compared to a GPU implementation [13]. The authors in [15] designed a decision tree classifier to recognize letters and digits. Xilinx Zynq SoC is used by the authors as a target hardware platform and Vivado high level synthesis is used as a development tool with C/C++ synthesis.…”

Section: Related Workmentioning

confidence: 99%

“…Xilinx Zynq SoC is used by the authors as a target hardware platform and Vivado high level synthesis is used as a development tool with C/C++ synthesis. Authors verified the correctness of the generated HDL code using C/RTL co-simulation [15].…”

Section: Related Workmentioning

confidence: 99%

FPGA Acceleration of Tree-based Learning Algorithms

Azmi¹

2020

Adv. sci. technol. eng. syst. j.

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Machine learning classifiers provide many promising solutions for data classification in different disciplines. However, data classification at run time is still a very challenging task for real-time applications. Acceleration of machine-learning hardware solutions is needed to meet the requirements of real-time applications. This paper proposes a new implementation of a machine learning classifier on Field Programmable Gate Arrays (FPGA). The proposed implementation utilizes the MicroBlaze soft-core processor on FPGA and uses the Advanced eXtensible Interface (AXI) bus to integrate the MicroBlaze with hardware peripherals. Experimental results shows that hardware-software co-design is a promising solution as it saves silicon area and provides a flexible configuration of decision tree algorithms at run time.

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FPGA Implementation of Decision Trees and Tree Ensembles for Character Recognition in Vivado Hls

Cited by 27 publications

References 14 publications

FPGA Accelerator for Gradient Boosting Decision Trees

FPGA Accelerator for Gradient Boosting Decision Trees

Implementation of decision tree algorithm on FPGA devices

FPGA Acceleration of Tree-based Learning Algorithms

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