FPGA implementation of enhanced key expansion algorithm for Advanced Encryption Standard

Gandh, D.Rahul; Kamalakannan, V.; Balamurugan, R.; Tamilselvan, S.

doi:10.1109/ic3i.2014.7019744

Cited by 13 publications

(10 citation statements)

References 4 publications

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“…Most of the AES processes are done in a particular finite field. Hence, if there are 16 bytes A0, A1, A2…A15 these bytes are represented as two dimensional arrays [4,16].…”

Section: Fig 1 the Aes Encryption Systems Steps Of Each Roundmentioning

confidence: 99%

“…However, the security of DES was reduced because of the short length key. Different attacks are capable of hacking DES in less than 255 complexities; in order to replace the DES it was important to find a stronger encryption algorithm [4,5]. It was interesting to find an alternative encryption method instead of DES to avoid the attacks.…”

Section: Introductionmentioning

confidence: 99%

“…The Rijndael algorithm was suitable for encryption so it became the standard. The AES algorithm was designed to increase the security level compared to the DES [4,5].…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of Pipelined AES Encryption System using FPGA

Nabil¹,

Khalaf²,

Hassan³

2020

IJRTE

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Nowadays, the data encryption became very important because of the usage of the data transmission in all the filed. The Advanced Encryption Standard (AES) that known as Rijndael algorithm is one of the most common encryption algorithms. The AES consists of 9 rounds in addition to the initial and final rounds that makes the AES consumes much time for encrypting the data. Of course the time consumption is considered one of the problems that face the information security. The more time the encryption system consumes to encrypt the data, the more chances increase for the hackers to break into the system. In this work, we find a new technique that can be used to increase the performance speed of the advanced encryption standard. The proposed algorithm methodology depends on the pipelined processing method for the processing time reduction. The paper includes a discussion of the design, the analysis and the implementation using Field Programmable Gate Array (FPGA) of the pipelined method to reduce the consumed numbers of clocks and speed up the processes. The AES is used to protect information and encrypt sensitive data and used in satellites, missiles, military application and other critical application. The paper describes the AES encryption system algorithm and the implementation of both the normal processing and the pipelined processing, and finally a comparison between the two algorithms.

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“…Most of the AES processes are done in a particular finite field. Hence, if there are 16 bytes A0, A1, A2…A15 these bytes are represented as two dimensional arrays [4,16].…”

Section: Fig 1 the Aes Encryption Systems Steps Of Each Roundmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design and Implementation of Pipelined AES Encryption System using FPGA

Nabil¹,

Khalaf²,

Hassan³

2020

IJRTE

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“…The Enhanced Key Expansion unit requires space for only storing one round key, and thus generates the round keys on the fly. The traditional key expansion algorithm is prone to saturation and power analysis attacks, hence, we instead employ enhanced key expansion algorithm [26] to generate round keys which is given in the equations (9)- (12):…”

Section: Enhanced Key Expansion Unitmentioning

confidence: 99%

FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach

Chawla

Goel

2015

2015 Annual IEEE India Conference (INDICON)

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As network technology advances, information security issues increase the need for developing low-area and lowpower high performance real-time processing of cryptographic algorithms. In this paper, we present a novel 8-bit architecture for Advanced Encryption Standard (AES) encryption which supports keys of 128-bit in length. The proposed architecture consists of a single round of ShiftRows, ByteSubstitution, MixColumns and AddRoundKey operations through which the data is iterated for ten rounds, which results in substantial reduction in terms of area and power consumption. We have proposed a new architecture for ByteSubstitution and AddRoundKey operations by employing high order masking and a different key expansion algorithm respectively, hence making the proposed architecture less vulnerable to Differential Power Analysis (DPA) and saturation attacks. Moreover, we have also utilized a new architecture for ShiftRows operation for further minimizing the area on chip. The proposed architecture was implemented on Virtex-7 FPGA using two different implementation strategies-Performance Explore and Area Explore using Vivado Design Suite. Using performance explore strategy, the proposed architecture worked at the maximum frequency of 200.32 MHz with a throughput of 160.26 Mbps, whereas, with area explore strategy, the proposed architecture utilized 662 slices, 796 LUTs and 0.303 Watt in power.

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“…It can both increase the difficulty of brute force AES and can effectively prevent the weaknesses of a variety of AES key expansion attack, and will not affect the speed of its 514 | P a g e www.ijacsa.thesai.org current run. [11]. In HLES algorithm, the key is divided to four parts of 128-bit that are expanded to occupy 10 rounds.…”

Section: B Key Expansion and Roundsmentioning

confidence: 99%

High Lightweight Encryption Standard (HLES) as an Improvement of 512-Bit AES for Secure Multimedia

Eddine¹,

Ouarda²,

Brahim³

2016

ijacsa

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Abstract-In today's scenario, people share information to another people frequently using network. Due to this, more amount of information are so much private but some are less private. Therefore, the attackers or the hackers take the advantage and start attempting to steal the information since 2001. the symmetric encryption algorithm called 512-bit AES provides high level of security, but it's almost be impossible to be used in multimedia transmissions and mobile systems because of the need for more design area that effect in the use of large memory space in each round and the big encryption time that it takes. This paper presents an improvement of 512-bit AES algorithm with efficient utilization of resources such as processor and memory space. The proposed approach resists the linear and differential encrypt analysis and provides high security level using a 512-bit size of key block and data block and ameliorates the performance by minimizing the use of memory space and time encryption to be able to work in specific characteristics of resource-limited systems. The experimental results on several data (text, image, sound, video) show that the used memory space is reduced to quarter, and the encryption time is reduced almost to the half. Therefore, the adopted method is very effective for encryption of multimedia data.

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FPGA implementation of enhanced key expansion algorithm for Advanced Encryption Standard

Cited by 13 publications

References 4 publications

Design and Implementation of Pipelined AES Encryption System using FPGA

Design and Implementation of Pipelined AES Encryption System using FPGA

FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach

High Lightweight Encryption Standard (HLES) as an Improvement of 512-Bit AES for Secure Multimedia

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