FPGA Implementation of Fixed-point Divider Using Pre-computed Values

Kasim, Muhammad; Adiono, Trio; Fahreza, Muhammad; Zakiy, Muhammad Fadhli

doi:10.1016/j.protcy.2013.12.182

Cited by 12 publications

(10 citation statements)

References 8 publications

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“…F. Zakiy discussed a divider block with pre-computed values stored in read-only memory in terms of a look-up table. This divider working is similar to that of dividers based on functional iteration type of algorithms like Goldschmidt's algorithm and Newton's method [16]. Thus, the result of this divider is also approximate value, unlike iterative subtraction class-based dividers.…”

Section: Implementation Statisticsmentioning

confidence: 83%

“…Slow type 2. Fast type Based on execution [16], we can classify types of dividers as 1. Iterative subtraction type 2. redictive type Various attempts have been made to study different division algorithms to state their quotient conversion logic, purpose, and design requirements [14], [17], covering some aspects of comparison.…”

Section: Division Algorithm Backgroundmentioning

confidence: 99%

“…The look-up table class is hybrid, in which look-up tables are utilized to improve different classes of algorithms; e.g., the look-up table can be used in the SRT algorithm to store the quotient bit selection table and in functional iteration class algorithms to store the elements required for initial approximation, which ultimately reduces the absolute error. Moreover, one more type of algorithm is discussed in [16], explaining the use of the look-up table for storing and utilizing pre-computed values to perform the division operation. In the algorithm, it first scales down the denominator in the range of 0.5 to 1; then it refers to the pre-computed value for the reciprocal of a scaled-down divisor to multiply with the numerator to get the quotient bit.…”

Section: Look-up Table Classmentioning

confidence: 99%

“…• If there is a need to increase the result's precision, one must find some ways to apply different operands' scaling techniques. In [16], Md. F. Kasim, T. Adiono, Md.…”

Section: Implementation Statisticsmentioning

confidence: 99%

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Review of Basic Classes of Dividers Based on Division Algorithm

Patankar

Koel

2021

IEEE Access

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The electronics world is very well described in two distinct but dependent interdisciplinary areas, namely hardware and software. Arithmetic operations are very vital building blocks of an electronic system. An algorithm is a systematic arrangement that helps develop a sophisticated electronic system, including hardware and software aspects. Addition, subtraction, multiplication, and division are critical elements of arithmetic implementation in the electronic system, but fewer efforts have been made to implement division than other arithmetic operations, even though the number of transistors on a chip is increasing beyond the Moore's law prediction. It is quite complicated to implement arithmetical operations; here, a sophisticated algorithm is essential to successful implementation. Technological upgrades are leading to a new paradigm of applications, where the performance of a division circuit or block is a vital and critical feature of a successful system. The lexicon of algorithms used in the implementation of the division operation in electronics systems is discussed in detail in the present article, which indicates the mathematical formulation, criticality, conversion pattern, hardware requirements, and logic used for conversion. The current report describes the broad classification of dividers into basic classes named digit recurrence, high radix, functional iteration, estimation, a look-up table, and variable latency. It also illustrates that, in practical implementation, many algorithms have been developed that combine one or many classes and are implemented with different hardware architectures. The study indicated the possibility of improving the presently available algorithms or creating a new algorithm to enhance practical implementation.

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Section: Implementation Statisticsmentioning

confidence: 83%

Section: Division Algorithm Backgroundmentioning

confidence: 99%

Section: Look-up Table Classmentioning

confidence: 99%

“…• If there is a need to increase the result's precision, one must find some ways to apply different operands' scaling techniques. In [16], Md. F. Kasim, T. Adiono, Md.…”

Section: Implementation Statisticsmentioning

confidence: 99%

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Review of Basic Classes of Dividers Based on Division Algorithm

Patankar

Koel

2021

IEEE Access

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“…In 27 , Kasim et al discussed a divider block with precomputed values stored in ROM in terms of a LUT. This divider operation is similar to the dividers based on functional iteration algorithms such as Goldschmidt's algorithm and Newton's method 27 . The result of this divider is also an approximate value, unlike those of iterative subtraction class-based dividers.…”

Section: Introductionmentioning

confidence: 99%

Novel data dependent divider circuit block implementation for complex division and area critical applications

Patankar

Flores

Koel

2023

Sci Rep

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This article elaborates on the state-of-the-art novel Udayan S. Patankar (USP)-Awadhoot algorithm for distinctive implementation area improvement for area-critical electronic applications. The proposed USP-Awadhoot divider is a digit recurrence class, but it can be flexibly implemented as a restoring or nonrestoring algorithm. The implementation example indicates the use of the Baudhayan-Pythagoras triplet method in association with the proposed USP-Awadhoot divider. The triplet method provides an easy way to generate Mat_Term1, Mat_Term2, and T_Term, which are further utilized with the proposed USP-Awadhoot divider. The USP-Awadhoot divider is implemented in three parts. First is preprocessing circuit stage for executing a dynamic separate scaling operation on input operands, ensuring the inputs are in the correct form. Second is the processing circuit stage for implementing the conversion logic expressed by the Awadhoot matrix, and third is the postprocessing circuit stage for recombining the individual results into the final result. The proposed divider works upto 285 MHz frequency with a power estimation of 3.366 W, also significantly improves the chip area requirements over those of the commercially and noncommercially implemented solutions.

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Scalable architecture of constant division on FPGA

Gorodecky,

Sousa

2023

2023 IEEE 30th Symposium on Computer Arithmetic (ARITH)

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FPGA Implementation of Fixed-point Divider Using Pre-computed Values

Cited by 12 publications

References 8 publications

Review of Basic Classes of Dividers Based on Division Algorithm

Review of Basic Classes of Dividers Based on Division Algorithm

Novel data dependent divider circuit block implementation for complex division and area critical applications

Scalable architecture of constant division on FPGA

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