FPGA implementation of K-means algorithm for bioinformatics application: An accelerated approach to clustering Microarray data

Hussain, Hanaa M.; Benkrid, Khaled; Şeker, Hüseyin; Erdogan, A.T.

doi:10.1109/ahs.2011.5963944

Cited by 79 publications

(47 citation statements)

References 11 publications

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“…The learning complexity is greatly related to the number of dimensions of the sample vectors. Thus, previously reported works [8,10] were difficult to be implemented in the highly dimensional applications. By using the proposed architecture, a larger number of dimensions and samples, even a higher learning speed were achieved with less complexity of hardware.…”

Section: Comparisonsmentioning

confidence: 99%

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An analog on-line-learning K-means processor employing fully parallel self-converging circuitry

Zhang

Shibata

2012

Analog Integr Circ Sig Process

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A hardware-efficient on-line-learnable processor was developed for the K-means clustering of highly dimensional vectors. Based on our proposed sample updating strategy, an incremental number of sample vectors can be clustered by a constant set of VLSI circuits. In order to speed up the learning process, we developed an analog fully parallel self-converging circuitry to implement the K-means algorithm. Upon receiving a sample vector on-line, the K-means learning autonomously proceeds and converges within a single system clock cycle (0.1 ls at 10 MHz). Furthermore, the chip-area and inner connection explosion problem was solved by using the proposed architecture. A proof-of-concept processor was designed and verified by the HSPICE and Nanosim simulations. The images from an actual database were used as learning samples in the form of 64 dimensional feature vectors. From the simulation results, all the samples were clustered into correct categories with a randomly ill initialization. In addition, the number of sample vectors can be freely increased.

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Section: Comparisonsmentioning

confidence: 99%

“…Several works employing digital VLSI circuits realized image segmentation based on the K-means algorithm [6][7][8][9]. In these approaches, the Manhattan distance was employed as a distance measure.…”

Section: Introductionmentioning

confidence: 99%

An analog on-line-learning K-means processor employing fully parallel self-converging circuitry

Zhang

Shibata

2012

Analog Integr Circ Sig Process

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“…It is a wellperceived fact in the research community that cluster analysis is primarily used for unsupervised learning where the class labels for the training data are not available. However, the K-Means algorithm can also be used for supervised learning where the class labels of the training data are known a priori [3]- [9]. Apart from using it as a learning algorithm, KMeans has also been utilized for signal pre-processing, feature reduction and time-domain signal analysis [2] .…”

Section: Introductionmentioning

confidence: 99%

“…This is generally achieved by the use of power hungry multipliers, square rooters (for Euclidean distance computation) and multiplexers [3]- [9], thereby rendering direct mapping of this algorithm to architecture infeasible for implementation on resource-constrained platforms. An attempt was made to replace the Euclidean distance by a combination of Manhattan and Max distance but by trading-off accuracy for power consumption in [10].…”

Section: Introductionmentioning

confidence: 99%

Coordinate Rotation-Based Low Complexity $K$ -Means Clustering Architecture

Adapa

Biswas

Bhardwaj

et al. 2017

IEEE Trans. VLSI Syst.

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Abstract-In this paper, we propose a low-complexity architectural implementation of the K-Means based clustering algorithm used widely in mobile health monitoring applications for unsupervised and supervised learning. The iterative nature of the algorithm, computing the distance of each data point from a respective centroid for a successful cluster formation until convergence presents a significant challenge to map it onto a lowpower architecture. This has been addressed by the use of a 2-D Coordinate Rotation Digital Computer (CORDIC) based lowcomplexity engine for computing the n-dimensional Euclidean distance involved during clustering. The proposed clustering engine was synthesized using the TSMC 130 nm technology library and a place and route was performed following which the core area and power were estimated as 0.36mm 2 and 9.21mW @ 100 Mhz respectively making the design applicable for low-power real-time operations within a sensor node.Index Terms-K-Means, CORDIC, signal processing, hardware design, low complex architecture.

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“…Recently, reconfigurable systems using FPGAs have been utilized for acceleration of specific applications including bio-informatics and financial problems [8,9]. Even though the early reconfigurable systems did not focus on large-scale numerical scientific application, the use of FPGAs for such areas has been growing remarkably because of the rapid performance improvement of modern FPGAs with a large number of configurable logic blocks, memory blocks and embedded multipliers.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration

Talip

Akamine

Hatto

et al. 2013

IJNC

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In aerospace industry, computational fluid dynamics (CFD) is used as a common design tool. Fast Aerodynamics Routines (FaSTAR) is one of the most recent CFD software package, convenient for users with various solvers and automatic generation of grid data. The problem of FaSTAR is hard to be executed in parallel machines because of its irregular and unpredictable data structure. Exploiting reconfigurable hardware with their advantages to make up for the inadequacy of the existing high performance computers had gradually become the solutions and trends. However, a single FPGA is not enough for the FaSTAR package because the whole module is very large. Instead of using a large number of chips, partially reconfigurable hardware available in recent FPGAs is explored for this application. Advection term computation module in FaSTAR is chosen as a target subroutine. We proposed a reconfigurable flux calculation scheme using partial reconfiguration technique to save hardware resources to fit in a single FPGA. We developed flux computational module and three flux calculation schemes are implemented as reconfigurable modules. This implementation has advantages of up to 42% resource saving and enhancing the configuration speed by 6.28 times. Performance evaluation also shows that 2.65 times acceleration is achieved compared to Intel Core 2 Duo at 2.4GHz.

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FPGA implementation of K-means algorithm for bioinformatics application: An accelerated approach to clustering Microarray data

Cited by 79 publications

References 11 publications

An analog on-line-learning K-means processor employing fully parallel self-converging circuitry

An analog on-line-learning K-means processor employing fully parallel self-converging circuitry

Coordinate Rotation-Based Low Complexity $K$ -Means Clustering Architecture

Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration

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