FPGA Implementation of Multiplier-Accumulator Unit using Vedic multiplier and Reversible gates

Rajesh, K.; Reddy, G. Umamaheswara

doi:10.1109/icisc44355.2019.9036345

Cited by 15 publications

(6 citation statements)

References 7 publications

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“…Mainly in this project, a reversible multiplier is used for testing using the reversible BILBO logic applied for finding two main faults SAF, MSAF, and MGF faults of the design. Stuck at faults are rare faults that occur in designs and can be more complexes to find the faults whether to zero or one, Multiple stuck at faults also a rare finding of faults in conventional designs and Missing gate fault changes the output of the design, finding these types of faults are the most important nowadays to make fault free system designs [30], [31].…”

Section: System Design and Testing Methodsmentioning

confidence: 99%

Design and testing of systolic array multiplier using fault injecting schemes

Jahagirdar

Rao

2022

Comput. Sci. Inf. Technol.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.

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Section: System Design and Testing Methodsmentioning

confidence: 99%

Design and testing of systolic array multiplier using fault injecting schemes

Jahagirdar

Rao

2022

Comput. Sci. Inf. Technol.

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“…Multiplication and accumulate operations are distinctive for digital filters. The MAC operations are also required for Fast Fourier Transforms [2]. Fig.…”

Section: Fig 1 Mac Unit Block Diagram [11]mentioning

confidence: 99%

“…MAC also has tremendous applications in audio and video signal processing, Artificial Intelligence (AI), machine learning, military and defense [1]. Since these operations require a cyclic application of multiplication and addition, the speed of execution depends on the overall performance of the MAC unit [2]. Using a MAC unit improves the accuracy and also reduces time delay for computing dot product, matrix multiplication, artificial neural networks, and various mathematical computations.…”

Section: Introductionmentioning

confidence: 99%

“…The author mentioned there is scope to improve the area constraint. Rajesh and Reddy have also compared various adder circuits, ripple carry adder (RCA), carry save adder(CSA), the kogge stone adder (KSA) and DKG gate adder in the paper using simulation carried out with Xilinx ISE 14.7.They concluded that DKG adder gate using a Vedic multiplier with reversible computing leads to significantly reduce the total time delay [2].Ozcan and Erdem have implemented Barrett in the paper, a multiplier using fast carry select adder, which uses less hardware [3]. Zhou et al have implemented FPGA based high-speed floating-point MAC which improves the performance of computing systems such as matrix multiplication and matrix vector multiplication [4].…”

Section: Introductionmentioning

confidence: 99%

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Design and Analysis of Multiplier Accumulator Circuit for DSP Applications

Frank¹,

Ramesh²

2022

International Journal of Advanced Science and Engineering

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“…1 Generic block which will give output of 128-bit data after positive multiplier analysis. These 128bit data multiplier outputs are supplied as an input to one add-on [13][14][15]. You can use three different types of adders here, one Kogge stone adder and a new HNFG gate.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Parallel Adder Using Reversible Logic Gates

Yuvaraj¹,

Gunasekaran²,

Muthukumaran

et al. 2021

Micro-Electronics and Telecommunication Engineering

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Reversible digital technology can now start taking a more desirable direction for low dissipation of power, higher processing speeds. Here, we suggested the construction of an 8-, 16-, 32-, 64-bit multiplier using the carry-save adder, the Kogge stone adder, and the HNFG adder with the high operating speed of the proposed HNFG gate adder. The architecture of the device and the logic gates which are reversible can be implemented using the Vedic multiplier. The output of the accumulator operation is dependent on the multiplier unit and the adder units. Here, the development of a multiplier and an adder can be built using reversible gates to achieve high operating speeds, and the use of a Vedic multiplier for greater efficiency. Also fewer area and partial elements are used. A comparative study is being conducted between the conventional [1] and the Kogge stone adder based on HNFG. Finally, it has been shown that the proposed HNFG gate with multiplier adder has a relatively high-speed over the conventional method. The whole process of simulation and synthesis is done using Xilinx 14.7 tool.

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FPGA Implementation of Multiplier-Accumulator Unit using Vedic multiplier and Reversible gates

Cited by 15 publications

References 7 publications

Design and testing of systolic array multiplier using fault injecting schemes

Design and testing of systolic array multiplier using fault injecting schemes

Design and Analysis of Multiplier Accumulator Circuit for DSP Applications

FPGA Implementation of Parallel Adder Using Reversible Logic Gates

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