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FinFet transistors are used in major semiconductor organizations and a significant role is played by it in developing the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, different algorithms such as PODEM (Path Oriented Decision Making algorithms) are used to find the fault detection and location. The Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this research work Combinational Circuits are designed using 20nm/32nm technology nodes in LT Spice environment and PODEM Algorithm is implemented which is developed in MATLAB, to detect and identify fault location and sensitive test vector to detect fault in the circuit and results are presented..

Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.

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