FPGA implementation of stream cipher using Toeplitz Hash function

Abstract

Hardware efficient stream ciphers and hash functions are widely used in cryptographic applications. The onewayness and low hardware complexity of hash function make it a good candidate for authentication operation of crypto-systems. On the other hand, stream ciphers are being widely used in the domain of cryptology. Generally, these stream ciphers use static key stream for the crypto process. In this work, we propose a hash function based key generator and integrate the hash function based key generation with the RC4 stream cipher block so as to provide dynamic key to the RC4's encryption system thus realizing a robust security hardware prototype. The proposed method is designed for 5-bit hash key and stream cipher using Verilog HDL and simulated using Xilinx ISE 14.2 simulator. Further the design implementation has been done on the commercially available Xilinx Spartan 3E fg320-4 FPGA device. The excellence of the generated random key value by our proposed method is validated using the statistical tests proposed by National Institute of Standard and Technology (NIST).

Quantum Leap and Crash

“…Zheng et al [24] propose a QRNG based on vacuum-fluctuation observations, which can reach output speed of 6 Gb/s of reliably random values. This device relies on Field-Programmable-Gate-Array (FPGA) implemented Toeplitz hashing [25] to achieve high-speed, real-time post-processing. Zheng et al state that their generator has a theoretical maximum speed of 12 Gb/s, but that information-theoretic randomness is only achievable at speed of 6 Gb/s.…”

Dynamic Hash key‐based stream cipher for secure transmission of real time ECG signal

“…The Toeplitz matrix has the characteristic property, by which each binary value of matrix column in the Toeplitz matrix is attained by accumulation new binary value to the initial value of the column and moving the values down to the preceding column . Thus, in the Toeplitz matrix, each of the following element of matrix column represents the next stages in feedback shift register of linear type.…”