Hardware efficient stream ciphers and hash functions are widely used in cryptographic applications. The onewayness and low hardware complexity of hash function make it a good candidate for authentication operation of crypto-systems. On the other hand, stream ciphers are being widely used in the domain of cryptology. Generally, these stream ciphers use static key stream for the crypto process. In this work, we propose a hash function based key generator and integrate the hash function based key generation with the RC4 stream cipher block so as to provide dynamic key to the RC4's encryption system thus realizing a robust security hardware prototype. The proposed method is designed for 5-bit hash key and stream cipher using Verilog HDL and simulated using Xilinx ISE 14.2 simulator. Further the design implementation has been done on the commercially available Xilinx Spartan 3E fg320-4 FPGA device. The excellence of the generated random key value by our proposed method is validated using the statistical tests proposed by National Institute of Standard and Technology (NIST).

In the last few decades, patients demand the data integrity and confidentiality of their Electrocardiography (ECG) signal for remote diagnosis through the network. In this context, a Dynamic Hash key‐based stream cipher for a cryptosystem is proposed to transmit the ECG signal to maintain integrity and confidentiality. The novelty of this proposed methodology is based on real‐time dynamic non‐recursive pseudorandom keystream using dynamic Toeplitz hash value‐based RC4 algorithm, unlike the existing static key‐based stream ciphers. The Toeplitz hash value (HV) is constructed from the sequence generated using non‐singular sequence folding‐based nonlinear feedback function expressed in algebraic normal form. The proposed design is realized using Verilog hardware description language (HDL) to construct the non‐recursive dynamic key stream sequence and prototyped on existing hardware Field‐programmable gate array (FPGA) device Virtex 5 xc5vlx110t‐2ff1136. The generated dynamic binary key stream sequence is analysed for key size, correlation and further verified by randomness tests using National Institute of Standards and Technology statistical test suites. The laboratory experiment is carried out with the existing two FPGA boards to prototype the proposed hardware cryptosystem for the encryption and decryption of real time ECG signal. The implementation result in the FPGA device accomplishes with the initial latency of 257 clock cycles and improved data throughput of 534Mbps than the existing design. Copyright © 2016 John Wiley & Sons, Ltd.

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