2011
DOI: 10.1016/j.aeue.2010.02.012
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FPGA implementation of vector directional distance filter based on HW/SW environment validation

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Cited by 9 publications
(5 citation statements)
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“…From Tab. 4, we can conclude that our design is more performant than [7,8,20] in spite of that the AVDDF is more complex than the VDF, DDF and VDDF filters.…”
Section: Hw/sw Experimental Resultsmentioning
confidence: 70%
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“…From Tab. 4, we can conclude that our design is more performant than [7,8,20] in spite of that the AVDDF is more complex than the VDF, DDF and VDDF filters.…”
Section: Hw/sw Experimental Resultsmentioning
confidence: 70%
“…The proposed design allows to speed up the VDF filtering process. In [8], an approximated hardware design is proposed to implement the VDDF filter. This architecture provides a good balance between the filtering quality and the processing time.…”
Section: Introductionmentioning
confidence: 99%
“…In addition, in Ref. [21], the classic VDDF filter is implemented to have a solution which can speed up the execution time while maintaining good accuracy. For that, the author can predict that the proposed implementation of the AVDDF filter gives better performances and can be used in many applications.…”
Section: Performance Evaluationmentioning
confidence: 99%
“…Further, the l parameter in (3) is selected equal to 0.75 and is chosen based on Refs. [20,21]. In fact, in Ref.…”
Section: Performance Evaluationmentioning
confidence: 99%
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