FPGA Implementaton of Strongly Parallel Histogram Equalization

Jamro, E.; Wielgosz, Maciej; Wiatr, K.

doi:10.1109/ddecs.2007.4295260

Cited by 14 publications

(14 citation statements)

References 2 publications

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“…There are ambiguities in mathematical description of technical state of machines. The application of a classifier based on neural networks enables the recognition of machines technical state when mathematical description is ambiguous [2][3][4]. Broad research on neural classifiers carried out recently indicates that artificial neural networks are promising alternative to conventional methods of classification [2,3,5,6].…”

Section: S(r θ) = E T {φ(S)mentioning

confidence: 99%

Hardware Implementation of Artificial Neural Networks for Vibroacoustic Signals Classification

Dąbrowski¹,

Jamro²,

Cioch³

2010

Acta Phys. Pol. A

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This paper studies the architecture of a neural classifier designed to identify technical condition of machines, based on vibroacoustic signals. The designed neural network is optimized for implementation on Field Programmable Gate Arrays (FPGA) programmable devices. FPGA allows massive parallelism and thus real-time classification as each neuron can execute arithmetic operations simultaneously. The classifier of vibroacoustic signals was designed and tested for the self -organized neural network. The teaching vectors are based on estimates derived from processed vibroacoustic signals generated by rotary machines. The created classifier was applied for recognizing technical state of demonstrative toothed gear DMA1 in variable operating conditions.

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Section: S(r θ) = E T {φ(S)mentioning

confidence: 99%

Hardware Implementation of Artificial Neural Networks for Vibroacoustic Signals Classification

Dąbrowski¹,

Jamro²,

Cioch³

2010

Acta Phys. Pol. A

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“…However, such systems can only achieve a speedup factor of up to two [44]. Similar approaches have been proposed for low speed data throughput, by [43]. This solution rely on the different clock speed between data input and FPGA system clock.…”

Section: Existent Hardware Implementationsmentioning

confidence: 99%

“…In order to speed up the above presented circuit to an evaluation per clock cycle, a dual port RAM solution has been presented in [42] and [43]. Dual port memory arrays are the common solution due to functional histogram behaviour.…”

Section: Existent Hardware Implementationsmentioning

confidence: 99%

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Reconfigurable FPGA architecture for computer vision applications in Smart Camera Networks

Maggiani¹,

Salvadori²,

Petracca³

et al. 2013

2013 Seventh International Conference on Distributed Smart Cameras (ICDSC)

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Smart Camera Networks (SCNs) is nowadays an emerging research field which represents the natural evolution of centralized computer vision applications towards full distributed and pervasive systems. In this vision, one of the biggest effort is in the definition of a flexible and reconfigurable SCN node architecture able to remotely update the application parameter and the performed computer vision application at runtime. In this respect, we present a novel SCN node architecture based on a device in which a microcontroller manage all the network functionality as well as the remote configuration, while an FPGA implements all the necessary module of a full computer vision pipeline. In this work the envisioned architecture is first detailed in general terms, then a real implementation is presented to show the feasibility and the benefits of the proposed solution. Finally, performance evaluation results underline the potential of an hardware software codesign approach in reaching flexibility and reduced processing time.

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“…The BRAM limits the calculation speed as the output data is one CLK delayed with respect to the address bus (a synchronous memory data read); hence, evaluating a single input pixel involves two CLK. Strong parallelization of the computations is possible [12], and the histogram computation needs 34 LUTs and 23 FFs.…”

Section: A Calculation Of Entropymentioning

confidence: 99%

Ultrafast Scalable Embedded DCT Image Coding for Tele-immersive Delay-Sensitive Collaboration

Panggabean¹,

Wielgosz²,

Øverby³

et al. 2013

IJACSA

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Abstract-A delay-sensitive, real-time, tele-immersive collaboration for the future requires much lower end-to-end delay (EED) for good synchronization than that for existing teleconference systems. Hence, the maximum EED must be guaranteed, and the visual-quality degradation must be graceful. Distributed Multimedia Plays (DMP) architecture addresses the envisioned collaboration and the challenges. We propose a DCT-based, embedded, ultrafast, quality scalable image-compression scheme for the collaboration on the DMP architecture. A parallel FPGA implementation is also designed to show the technical feasibility.

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FPGA Implementaton of Strongly Parallel Histogram Equalization

Cited by 14 publications

References 2 publications

Hardware Implementation of Artificial Neural Networks for Vibroacoustic Signals Classification

Hardware Implementation of Artificial Neural Networks for Vibroacoustic Signals Classification

Reconfigurable FPGA architecture for computer vision applications in Smart Camera Networks

Ultrafast Scalable Embedded DCT Image Coding for Tele-immersive Delay-Sensitive Collaboration

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