FPGA Investigation on Error-Flare Performance of a Concatenated Staircase and Hamming FEC Code for 400G Inter-Data Center Interconnect

Cai, Yi; Wang, Weiming; Qian, Weixing; Xing, Jia; Tao, Kai; Yin, Junjie; Zhang, Shihua; Lei, Ming; Sun, Erkun; Chien, Hung‐Chang; Liao, Qun; Yang, Kè; Chen, Huan

doi:10.1109/jlt.2018.2881924

Cited by 25 publications

(11 citation statements)

References 15 publications

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“…After decomposing the RM (4,6) [16], and the synthesis results on a Xilinx Artix-7 FPGA were presented. In [9], Chase decoding of the 400G ZR (128,119) Hamming code was implemented. We design and implement a Chase decoder for the same code.…”

Section: Related Workmentioning

confidence: 99%

“…To improve the performance further, soft-decision (SD) FECs are studied and proposed, at the expense of increased complexity. One approach is concatenated coding using a SD inner code and a HD outer code [7], as in the 400G ZR implementation, recently specified by the Optical Interconnect Forum (OIF) [8], [9]. This system combines an inner SD-Hamming code with a HD outer staircase code in a 16 Quadrature Amplitude Modulation (QAM) optical communication system targeted at Data Center Interconnects (DCIs).…”

Section: Introductionmentioning

confidence: 99%

“…We consider the case where the SD-Hamming code is intended as the inner code in a concatenated coding scheme (Fig. 1), as in OIF 400G ZR [8], [9], where the outer code is a HD staircase code. We set the 4.5 × 10 −3 output BER of the inner code as our target to match the 10 −15 output BER of an outer staircase code, as is specified in [1] at the overhead ∼ 6.7%.…”

Section: Introductionmentioning

confidence: 99%

“…Higher BER can also be relevant, if relaxing the BER requirement after outer code [1] or allowing a higher overhead [10]. An implementation of 400G ZR based on 50 FPGAs was presented in [9] for verification and investigation. This implementation had a throughput of 200 Gb/s.…”

Section: Introductionmentioning

confidence: 99%

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Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication

Zhang

Forchhammer

Andersen

et al. 2020

GLOBECOM 2020 - 2020 IEEE Global Communications Conference

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In this paper, we consider fast decoding of soft-decision (SD) Hamming codes as inner codes in concatenated forward error-correction (FEC) schemes for high-speed optical communication. The goal is single FPGA implementations at speeds of 400 Gb/s and beyond. A low complexity maximum a posteriori (MAP) probability decoding is applied to a (128,120) Hamming code. Chase decoding of a (128,119) Hamming code is also implemented. The VHDL designs for both decoding schemes are presented. The FEC performance and FPGA resource utilization are investigated and compared. Synthesis results indicate that, both the Chase and the MAP decoder leave sufficient resources available to also accommodate a powerful outer hard decision code, on a single FPGA. Furthermore, MAP decoding of (128,120) Hamming code features lower hardware complexity and provides a higher data throughput.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication

Zhang

Forchhammer

Andersen

et al. 2020

GLOBECOM 2020 - 2020 IEEE Global Communications Conference

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“…The concatenated Hamming-staircase code with an outer decoder error floor below 10 −15 is adopted as the 400ZR FEC algorithm, because of its well-balanced FEC performance and a low-complexity soft-decision Hamming code [22]. In [20], the performance of the 400ZR FEC was investigated down to BER of 10 −15 using FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Flexible Multilevel Coding with Concatenated Polar-Staircase Codes for M-QAM

Mehmood

Yankov

Iqbal

et al. 2020

IEEE Trans. Commun.

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In this work, a multilevel coding (MLC) based coded modulation scheme with two degrees of freedom in rate flexibility is proposed and compared with a bit-interleaved coded modulation (BICM) scheme from a performance versus complexity perspective. The proposed MLC scheme is based on a rate flexible inner soft-decision polar code and utilizes an outer hard-decision staircase code structure as in the 400ZR concatenated forward error-correcting code. The performance of the MLC scheme is investigated for a range of inner code lengths, inner decoder list sizes, and signaling with 16 and 64 quadrature amplitude modulation, respectively. The MLC is designed such that a portion of the staircase encoded bits can bypass the inner code. The number of required inner soft-decision decoders can thus be reduced, thereby saving computational complexity. The proposed MLC scheme simultaneously offers up to a 53.7% reduction in the number of inner decoders and up to 0.55 dB of performance improvement when compared with the similar BICM approach.

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FPGA-based 100G network readout solution for SHINE pixel detector

Zhang

Jiang

et al. 2022

Nuclear Instruments and Methods in Physics Research Section A:

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FPGA Investigation on Error-Flare Performance of a Concatenated Staircase and Hamming FEC Code for 400G Inter-Data Center Interconnect

Cited by 25 publications

References 15 publications

Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication

Fast SD-Hamming Decoding in FPGA for High-Speed Concatenated FEC for Optical Communication

Flexible Multilevel Coding with Concatenated Polar-Staircase Codes for M-QAM

FPGA-based 100G network readout solution for SHINE pixel detector

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