FPGA²: An open source framework for FPGA-GPU PCIe communication

Abstract

In recent years two main platforms emerged as powerful key players in the domain of parallel computing: GPUs and FPGAs. Many researches investigate interaction and benefits of coupling them with a general purpose processor (CPU), but very few, and only very recently, integrate the two in the same computational system. Even less research are focusing on direct interaction of the two platforms [1]. This paper presents an open source framework enabling easy integration of GPU and FPGA resources; Our work provides direct data transfer between the two platforms with minimal CPU coordination at high data rate and low latency. Finally, at the best of our knowledge, this is the first proposition of an open source implementation of a system including an FPGA and a GPU that provides code for both sides.Notwithstanding the generality of the presented framework, we present in this paper an actual implementation consisting of a single GPU board and a FPGA board connected through a PCIe link. Measures on this implementation demonstrate achieved data rate that are close to the theoretical maximum.

A Survey of the Heterogeneous Computing Platform and Related Technologies

“…FPGA +GPU architecture [3] is the collaboration of FPGA and GPU. FPGA chip is suitable for dealing with task of pipeline and GPU is suitable for the task of high parallelism.…”

Adaptive multispectral GPU accelerated architecture for Earth Observation satellites

“…Whilst GPU's and FPGA's are often compared against each other as hardware accelerators and are rarely utilised in the same system, interest in the area of GPU-FPGA heterogeneous computing and its potential application is a growing field of research [21]. The proposed new hardware architecture is based around a physical backplane, which connects different hardware devices chosen to handle specific stages in the onboard data processing chain.…”

FPGA-GPU communicating through PCIe

“…Design 1, as presented in [12], offered an input and an output FIFO to help the designer with the realization of streaming applications. It was conceived with a memory mapping allowing the central CPU to access the FIFOs through a range of addresses.…”

“…The most important blocks of the design 1 are described in [12]. Here we focus on the design 2, showing some differences with its ancestor:…”