FPGA modeling of diverse superscalar processors

Abstract

There is increasing interest in using Field Programmable Gate Arrays (FPGAs) as platforms for computer architecture simulation. This paper is concerned with modeling superscalar processors with FPGAs. To be transformative, the FPGA modeling framework should meet three criteria.(1) Configurable: The framework should be able to model diverse superscalar processors, like a software model. In particular, it should be possible to vary superscalar parameters such as fetch, issue, and retire widths, depths of pipeline stages, queue sizes, etc.(2) Automatic: The framework should be able to automatically and efficiently map any one of its superscalar processor configurations to the FPGA. (3) Realistic: The framework should model a modern superscalar microarchitecture in detail, ideally with prototype quality, to enable a new era and depth of microarchitecture research. A framework that meets these three criteria will enjoy the convenience of a software model, the speed of an FPGA model, and the experience of a prototype. This paper describes FPGA-Sim, a configurable, automatically FPGAsynthesizable, and register-transfer-level (RTL) model of an out-of-order superscalar processor. FPGA-Sim enables FPGA modeling of diverse superscalar processors out-of-the-box. Moreover, its direct RTL implementation yields the fidelity of a hardware prototype.

Fased

“…While the trends described in the previous section solve the availability and FPGA capacity challenges, usability remains a problem. Previous work [7,12] has shown that much of an FPGA-accelerated simulator can be automatically generated from source RTL. This Session 9: Memory FPGA '19, February 24-26, 2019, Seaside, CA, USA RTL can be written in an HDL like Verilog, generated by a high-level synthesis tool, or emitted by languages like Chisel [3] or Bluespec.…”

Energy Efficient Dual Issue Embedded Processor

“…The majority of academic research in the area of embedded processor architecture focuses on superscalar techniques, with some of the work specifically targeting FPGA implementation [10]. Some of the works investigated the use of simple scalar cores in multi-core processors targeting standard-cell implementations [11] as well as FPGA [13] to speed up the execution of multi-threaded applications.…”

“…Adding three or more ports requires the design of custom memories. An alternative solution is to emulate multi-read and multi-write memories using basic two port memories [10]. There are three different techniques, depicted in Figure 8, for emulating multi-port memories using standard dual-port memories:…”

“…Decoding and executing two instructions simultaneously each cycle requires two writes and four reads to the register file, which is double the number of ports used in the single issue processor. The method used for the single issue processor can be used for the dual issue processor but the implementation becomes more complex [10].…”

Towards an Area-Efficient Implementation of a High ILP EDGE Soft Processor

“…Design studies targeting higher instruction level parallelism (ILP) microarchitectures typically implement VLIW [5], [6] or vector [7], [8] architectures instead of out-of-order (OoO) [9]- [11] soft processor cores. The problem with superscalar OoO microarchitectures is the complexity of the machinery needed to rename registers, schedule instructions in dataflow order, clean up after mispeculation, and retire results in-order for precise exceptions.…”