FPGA placement and routing

Chen, Shih-Chun; Chang, Yao‐Wen

doi:10.1109/iccad.2017.8203878

Cited by 19 publications

(6 citation statements)

References 38 publications

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“…Based on analytical placement techniques, the FPGA placement problem is modeled as a continuous optimization problem, and the optimal solution of the placement problem is obtained by gradient descent. Analytical placement generally includes three main stages: global placement, legalization, and detailed placement [5]. Global placement calculates the optimal position of each module with wire length and other indicators as optimization goals, ignoring the nonoverlapping constraints of blocks.…”

Section: Related Workmentioning

confidence: 99%

Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization

Yu,

Guo

2023

Electronics

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The simulated annealing algorithm is an extensively utilized heuristic method for heterogeneous FPGA placement. As the application of neural network models on FPGAs proliferates, new challenges emerge for the traditional simulated annealing algorithm in terms of timing. These challenges stem from large circuit sizes and high heterogeneity in the block proportions typical in neural networks. To address these challenges, this study introduces a timing-driven simulated annealing placement algorithm. This algorithm integrates cluster criticality identification during the cluster selection phase, which enhances the probability of high-criticality cluster selection. In the cluster movement phase, the proposed method employs an improved weighted center movement for high-criticality clusters and a random movement strategy for other clusters. Experimental evidence demonstrates that the proposed placement algorithm decreases the average wire length by 1.52% and the average critical path delay by 5.03%. This improvement in performance is achieved with a marginal increase of 5.01% in runtime, as compared to VTR8.0.

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Section: Related Workmentioning

confidence: 99%

Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization

Yu,

Guo

2023

Electronics

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“…Farooq et al apply the time-multiplexing technology to multi-FPGA prototyping routing for more complicated designs [18] . Omam et al use RRAM-based switches and decrease 56% path delay compared to CMOS base switches [19] . Chen et al explore state-of-the-art research directions for FP-GA placement and routing [20] .…”

Section: Related Workmentioning

confidence: 99%

A routing algorithm for FPGAs with time-multiplexed interconnects

Luo¹,

Chen²,

Ha³

2020

J. Semicond.

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Previous studies show that interconnects occupy a large portion of the timing budget and area in FPGAs. In this work, we propose a time-multiplexing technique on FPGA interconnects. In order to fully exploit this interconnect architecture, we propose a time-multiplexed routing algorithm that can actively identify qualified nets and schedule them to multiplexable wires. We validate the algorithm by using the router to implement 20 benchmark circuits to time-multiplexed FPGAs. We achieve a 38% smaller minimum channel width and 3.8% smaller circuit critical path delay compared with the state-of-the-art architecture router when a wire can be time-multiplexed six times in a cycle.

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“…Field Programmable Gate Array (FPGA) is a semi-custom circuit, and the hardware description language will be converted into actual functions, after process mapping, placement and wiring, and other processes [1] . Legalization in FPGAs is the process of matching placement results to actual resources.…”

Section: Introductionmentioning

confidence: 99%

A Legalization Algorithm for Heterogeneous FPGAs

Dou,

Liang,

2023

J. Phys.: Conf. Ser.

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Heterogeneous cells are cells with special functions in Field-Programmable Gate Arrays (FPGA) and gradually become an important resource of FPGA chips. The legalization algorithm is a key step in resolving the global placement results of heterogeneous cells to their actual locations. The algorithm in this paper is improved on the abacus algorithm. We use subspaces to evaluate the degree of congestion of cells and sort them, and use optional columns to filter to achieve a reasonable allocation of resources. The experimental results show that our work has less average moving and worst movement in the case of high density and complex distribution.

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FPGA placement and routing

Cited by 19 publications

References 38 publications

Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization

Timing-Driven Simulated Annealing for FPGA Placement in Neural Network Realization

A routing algorithm for FPGAs with time-multiplexed interconnects

A Legalization Algorithm for Heterogeneous FPGAs

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