Fragmented software‐based self‐test technique for online intermittent fault detection in processors

Abstract

Software-based self-test (SBST) method is one of the widely used test techniques in processors. SBSTscheme provides high fault coverage but incurs long detection latencies in case of intermittent faults (IFs) in online testing mode, due to large size and longer execution time of the test codes. A study of fragmented SBST testing approaches is conducted to select the most efficient fragmented testing strategy. For the selected fragmented SBST method, a reliable set of SBST code fragments with minimal fault detection latency is determined. However, it incurs inconsiderable overall fault coverage drop, compared to the coverage of the complete SBST test code. From experimental results on MIPS Processor, a set of 20 fragments of test tasks with 80% individual fault coverage was observed to have the highest reliability of all sets of fragments. A larger test task (i.e. complete SBST test code) with 96.3% coverage and a test period of 8 ms was replaced by these 20 fragments, which provided an overall coverage of 96% with an individual test period of 0.4 ms, to detect the same set of IFs.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

Simulation and empirical validation of new sensitivity based reliability analysis technique for processors deployed in industrial drives

“…The electrical and logical masking are, respectively, given in Figure 4(c) and (d). Further, for the researcher’s knowledge, the detailed processor’s sensitivity faults are tabulated in Table 2 (Suryasarman et al , 2021). Table 2 includes characteristics, typical faults and causes of respective TFs, IFs and others.…”