Framework for Design Exploration and Performance Analysis of RF-NoC Manycore Architecture

Lahdhiri, Habiba; Lorandel, Jordane; Monteleone, Salvatore; Bourdel, Emmanuelle; Palesi, Maurizio

doi:10.3390/jlpea10040037

Cited by 8 publications

(6 citation statements)

References 21 publications

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“…NCSC uses N-shuffle stages connected by N crossbar network-based clusters; each consists of N processors. Nshuffle stages have been used before in many interconnection networks [21][22][23]. This scheme has been modified to an N-conjugate shuffle to meet the design needs of multi-cluster connection, where the conjugate core (manager core) in each cluster is responsible for inter-cluster communication.…”

Section: The Component Of the Proposed Schemementioning

confidence: 99%

A Scalable Interconnection Scheme in Many-Core Systems

Abumwais,

Eleyat

2023

CMC

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Recent architectures of multi-core systems may have a relatively large number of cores that typically ranges from tens to hundreds; therefore called many-core systems. Such systems require an efficient interconnection network that tries to address two major problems. First, the overhead of power and area cost and its effect on scalability. Second, high access latency is caused by multiple cores' simultaneous accesses of the same shared module. This paper presents an interconnection scheme called N-conjugate Shuffle Clusters (NCSC) based on multi-core multicluster architecture to reduce the overhead of the just mentioned problems. NCSC eliminated the need for router devices and their complexity and hence reduced the power and area costs. It also resigned and distributed the shared caches across the interconnection network to increase the ability for simultaneous access and hence reduce the access latency. For intra-cluster communication, Multi-port Content Addressable Memory (MPCAM) is used. The experimental results using four clusters and four cores each indicated that the average access latency for a write process is 1.14785 ± 0.04532 ns which is nearly equal to the latency of a write operation in MPCAM. Moreover, it was demonstrated that the average read latency within a cluster is 1.26226 ± 0.090591 ns and around 1.92738 ± 0.139588 ns for read access between cores from different clusters.

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Section: The Component Of the Proposed Schemementioning

confidence: 99%

A Scalable Interconnection Scheme in Many-Core Systems

Abumwais,

Eleyat

2023

CMC

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“…Inspired by Lahdhiri et al ( 2020 ) and Balaji et al ( 2020 ), we therefore created McAERsim as well as a patched version of the NoC simulator Noxim (Catania et al, 2015 ) that accept spike traces generated by the generic neuroscientific development environment NEST (Gewaltig and Diesmann, 2007 ). In Lahdhiri et al ( 2020 ), a framework combining the system level simulator Sniper (Carlson et al, 2011 ) with the NoC simulator Noxim is proposed to collect statistics regarding network traffic as well as energy consumption caused by application defined communication patterns. However, the released version of Noxim expects a traffic table for this purpose, which solely contains a packet injection rate for each source / destination pair.…”

Section: Introductionmentioning

confidence: 99%

NoC simulation steered by NEST: McAERsim and a Noxim patch

Robens,

Kleijnen,

Schiek

et al. 2024

Front. Neurosci.

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IntroductionGreat knowledge was gained about the computational substrate of the brain, but the way in which components and entities interact to perform information processing still remains a secret. Complex and large-scale network models have been developed to unveil processes at the ensemble level taking place over a large range of timescales. They challenge any kind of simulation platform, so that efficient implementations need to be developed that gain from focusing on a set of relevant models. With increasing network sizes imposed by these models, low latency inter-node communication becomes a critical aspect. This situation is even accentuated, if slow processes like learning should be covered, that require faster than real-time simulation.MethodsTherefore, this article presents two simulation frameworks, in which network-on-chip simulators are interfaced with the neuroscientific development environment NEST. This combination yields network traffic that is directly defined by the relevant neural network models and used to steer the network-on-chip simulations. As one of the outcomes, instructive statistics on network latencies are obtained. Since time stamps of different granularity are used by the simulators, a conversion is required that can be exploited to emulate an intended acceleration factor.ResultsBy application of the frameworks to scaled versions of the cortical microcircuit model—selected because of its unique properties as well as challenging demands—performance curves, latency, and traffic distributions could be determined.DiscussionThe distinct characteristic of the second framework is its tree-based source-address driven multicast support, which, in connection with the torus topology, always led to the best results. Although currently biased by some inherent assumptions of the network-on-chip simulators, the results suit well to those of previous work dealing with node internals and suggesting accelerated simulations to be in reach.

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“…Communications between clusters takes place through the Radio Frequency (RF) waveguides of the RHs. Within clusters, communication takes place over a mesh interconnection network (Lahdhiri et al, 2020).…”

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confidence: 99%

On Allocation Algorithms for Manycore Systems With Network on Chip

Shdefat

Bani-Mohammad

Ababneh

2023

International Journal of Grid and High Performance Computing

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Single-chip multicore processors and their network on chip interconnection mechanisms have received extensive interest since the early 2000s. The mesh topology is popular in networks on chip. A common issue in mesh is that it can result in high energy consumption and chip temperatures. It has been recently shown that mapping communicating tasks to neighboring cores can reduce communication delays and the associated power consumption and improve throughput. This paper evaluates the contiguous allocation strategy first fit and non-contiguous allocation strategies that attempt to achieve a degree of contiguity among the cores allocated to a job. One of the non-contiguous strategies is a new strategy, referred to as neighbor allocation strategy, which decomposes the job request so that it can be accommodated by free core submeshes and individual cores that have degree of contiguity. The results show that the relative merits of the policies depend on the job's communication pattern.

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Framework for Design Exploration and Performance Analysis of RF-NoC Manycore Architecture

Cited by 8 publications

References 21 publications

A Scalable Interconnection Scheme in Many-Core Systems

A Scalable Interconnection Scheme in Many-Core Systems

NoC simulation steered by NEST: McAERsim and a Noxim patch

On Allocation Algorithms for Manycore Systems With Network on Chip

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