This paper presents a dynamic simulation methodology using a reduced order compact macromodel of standard cells. The standard cell macromodels are formulated with a smaller number of state variables compared to an equivalent transistor-level implementation. This results in significant speed-ups over transistor-level simulation for large scale circuits. Such reduction in state variables also reduces memory usage. The macromodels are based on transistor equations, and simulation using these models produces results in excellent agreement (delay errors below 1 %) with transistor-level simulation results. Various examples showing 1.5x-lOOx reduction in dynamic simulation time and 1.5x-2.8x reduction in memory usage are presented.
INTRODUCTIONWith continuous technology scaling and increasing demand for more functionality per chip, the number of transistors per chip is increasing. This is making transistor-level simulation of VL SI circuits challenging because of increased simulation runtimes and memory requirements. Given that the transistor-level simulation is capable of producing the most accurate results, in order to alleviate the computational and memory burden of a full-chip simulation of today ' s VLSI circuits, a simulation methodology is required which can produce sufficiently accurate results while significantly lowering computational and storage cost compared to transistor-level simulation.