Frequency dependence of soft error rates for sub-micron CMOS technologies

Seifert, N.; Zhu, Xiao‐Wei; Moyer, D.; Mueller, R.W.; Hokinson, R.; Leland, N.; Shade, M.; Massengill, L.W.

doi:10.1109/iedm.2001.979501

Cited by 56 publications

(20 citation statements)

References 5 publications

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“…Since the charge collection process is fairly independent of the node size, as reported in [25,26], a good approximation to the collected charge probability density function is given by an exponential function of the form prob(Q) = a exp(ÀbQ), where a and b are fitting parameters. By replacing prob(Q) into Eq.…”

Section: Soft Error Rate (Ser)mentioning

confidence: 99%

See 1 more Smart Citation

Detailed 8-transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies

Bota

Torrens

Verd

et al. 2015

Solid-State Electronics

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Section: Soft Error Rate (Ser)mentioning

confidence: 99%

“…The SER of a circuit is defined as the sum of SER n over the total number of nodes [25]. There are two sensitive nodes in the 6T and 8T-cells: Node 1 and Node 2 ( Fig.…”

Section: Soft Error Rate (Ser)mentioning

confidence: 99%

Detailed 8-transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies

Bota

Torrens

Verd

et al. 2015

Solid-State Electronics

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“…Roughly speaking, flip-flops can latch SEUs every time the latching clock-edge is triggered. Therefore, an increase in operating frequency increases the frequency of latching opportunities [111]. Additionally, as power-supply voltage decreases and gate sizes shrink, fewer SEUs are expected to be attenuated.…”

Section: Additional Masking Mechanismsmentioning

confidence: 99%

Design, Analysis and Test of Logic Circuits Under Uncertainty

Krishnaswamy¹,

Markov²,

Hayes³

2013

Lecture Notes in Electrical Engineering

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“…Occurrence of SEUs in SRAM memories is increasing and becoming more critical as technology continues to shrink [7], [12], [13]. Shivakumar et al have predicted that an SER of combinational logic would increase to be comparable to the SER per chip of memory components in the future [14].…”

Section: Introductionmentioning

confidence: 97%

Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints

Sugihara

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor for computer systems so that we evaluate reliability of a task over various processor configurations. Next we build a mixed integer linear programming (MILP) model for minimizing chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.

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Frequency dependence of soft error rates for sub-micron CMOS technologies

Cited by 56 publications

References 5 publications

Detailed 8-transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies

Detailed 8-transistor SRAM cell analysis for improved alpha particle radiation hardening in nanometer technologies

Design, Analysis and Test of Logic Circuits Under Uncertainty

Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints

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