From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations

Abstract

This paper presents a seamless flow of transformations which performs dedicated distributed executive generation from a high level specification of a pair: algorithm, architecture. This work is based upon graph models and graph transformations and is part of the AAA methodology. We present an original architecture model which allows to perform accurate sequencer modeling, memory allocation, and heterogeneous inter-processor communications for both modes shared memory and message passing. Then we present the flow of transformations that leads to the automatic generation of dedicated real-time distributed executives which are deadlock free. This transformation flow has been implemented in a system level CAD software tool called SynDEx.

Reconciling performance and predictability on a many-core through off-line mapping

“…Previous work on off-line real-time scheduling [9], [10] has shown that tablebased techniques allow an efficient allocation of resources in multi-processor architectures, especially if classical optimization techniques such as software pipelining are used [11]. The main difference with respect to this work is that we take into account architectural aspects that are specific to manycores, such as the NoC-based communication system based on wormhole routing and with limited buffering capabilities.…”

Scientific Foundations

“…communication operations) described in the implementation graph. Thus, this graph is translated in an "executive graph" [28] where new vertices and edges are added in order to manage the infinite and finite loops, the conditionings, the inter-operator data dependences corresponding to "read" and "write" when the communication medium is a RAM, or to "send" and "receive" when the communication medium is a SAM. Specific vertices, called "pre" and "suc", which manage semaphores, are added to each read, write, send and receive vertices in order to synchronize the execution of operations and of communication operations when they must share, in mutual exclusion, the same sequencer as well as the same data.…”

From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations

“…We simplify it here according to our stateless abstraction: 5 The intuition behind weak endochrony is that we are looking for systems where (1) all causality is implied by the sequencing of messages on communication channels, and (2) all choices are visible as choices over the value (and not present/absent status) of some message. As explained in [10], the axioms of weak endochrony can be traced down to the fundamental result of Keller [7] on the deterministic operation of a system in an asynchronous environment.…”