1990
DOI: 10.1109/54.60603
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From behavior to structure: high-level synthesis

Abstract: In this tutorial, the author describes how high-level synthesis bridges the gap between behavioral specifications and hardware structure by automatically generating a circuit description from a netlist. The resulting description can be used for other design automation tools such as logic synthesis and layout. Describing high-level synthesis for synchronous digital hardware, the author explains the steps of the process, which include compilation, transformation, scheduling, and allocation.igh-level synthesis br… Show more

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Cited by 52 publications
(15 citation statements)
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“…Though traditional focus for efficient embedded processor implementation has been on optimizing code-generation techniques and hence relevant compiler technology, high-level transformations have started gaining importance because of their inherent portability and resultant boost in performance when applied appropriately ( [29], [50]). The nature of transformations can be of various kinds such as algorithmic or architectural [59], source-to-source [30] and have been studied in various contexts such as VLSI synthesis [18], DSP software synthesis [78], fault detection in parallel system [33] and so on.…”
Section: Modeling and Transformationsmentioning
confidence: 99%
See 1 more Smart Citation
“…Though traditional focus for efficient embedded processor implementation has been on optimizing code-generation techniques and hence relevant compiler technology, high-level transformations have started gaining importance because of their inherent portability and resultant boost in performance when applied appropriately ( [29], [50]). The nature of transformations can be of various kinds such as algorithmic or architectural [59], source-to-source [30] and have been studied in various contexts such as VLSI synthesis [18], DSP software synthesis [78], fault detection in parallel system [33] and so on.…”
Section: Modeling and Transformationsmentioning
confidence: 99%
“…After the cluster hierarchy is constructed, a schedule for the overall PSDF graph is derived by recursive traversal of the cluster hierarchy and subsets of the schedules associated with each clustered subgraph [18].…”
Section: Clustering In Sdf and Psdf Graphsmentioning
confidence: 99%
“…Loop unrolling is a standard compilation technique, both in software compilation and in synthesis from high level languages [1]. It could, in principle, be one approach to expanding a linear structure up to the capacity of the FPGA.…”
Section: Array Growth -Not Just Loop Unrollingmentioning
confidence: 99%
“…For more than twenty years, designing digital circuits at the Register Transfer Level (RTL) has been one of the key bottlenecks to productivity, and researchers have strived to raise the design abstraction level [2]. Progress in the area of High-Level Synthesis (HLS) has been less steady than originally anticipated, with various generations of tools reaching the market [7] and perhaps only in the last few years achieving some concrete commercial successes.…”
Section: Introductionmentioning
confidence: 99%