Sizing of Processing Arrays for FPGA-Based Computation

VanCourt, T.; Herbordt, Martin C.

doi:10.1109/fpl.2006.311307

Cited by 6 publications

(2 citation statements)

References 16 publications

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“…First of all, the tasks benefiting from acceleration are quite varied, affecting the dimensions of resulting circuit, which is often composed of variable number of computing elements organized into multidimensional arrays, trees etc. [4].…”

Section: Introductionmentioning

confidence: 95%

Architecture model for approximate tandem repeat detection

Martínek

Lexa

2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

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Algorithms for biological sequence analysis, such as approximate string matching or algorithms for identification of sequence patterns supporting specific structural elements, present good opportunities for hardware acceleration. Implementation of these algorithms often results in architectures based on multidimensional arrays of computing elements. Mapping effectively these computational structures on FPGAs remains one of the challenging problems. This paper focuses on a specific hardware architecture for detection of approximate tandem repeats in sequences. We show how to create a parametrized architecture model combined with an automatic technique that can determine appropriate circuit dimensions with respect to input task parameters and the target platform properties.

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Section: Introductionmentioning

confidence: 95%

Architecture model for approximate tandem repeat detection

Martínek

Lexa

2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

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“…12 FPGA capacity has terms for each of the available hardware resources, including hard multipliers and BRAMs as well as general-purpose logic elements. Depending on the application, any of the resources can become the limiting one.…”

Section: Methods 12: Scale Application For Maximal Use Of Fpga Hardwarementioning

confidence: 99%

Achieving High Performance with FPGA-Based Computing

et al. 2007

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Numerous application areas, including bioinformatics and computational biology, demand increasing amounts of processing capability. In many cases, the computation cores and data types are suited to field-programmable gate arrays. The challenge is identifying the design techniques that can extract high performance potential from the FPGA fabric.Accelerating high-performance computing (HPC) applications with field-programmable gate arrays (FPGAs) can potentially deliver enormous performance. A thousand-fold parallelism is possible, especially for low-precision computations. Moreover, since control is configured into the logic itself, overhead instructions-such as array indexing and loop computationsneed not be emulated, and every operation can deliver payload.At the same time, using FPGAs presents significant challenges 1 including low operating frequency-an FPGA clocks at one-tenth that of a high-end microprocessor. Another is simply Amdahl's law: To achieve the speedup factors required for user acceptance of a new technology (preferably 50 times), 2 at least 98 percent of the target application must lend itself to substantial acceleration. As a result, HPC/FPGA application performance is unusually sensitive to the implementation's quality.The problem of achieving significant speedups on a new architecture without expending exorbitant development effort, and while retaining flexibility, portability, and maintainability, is a classic one. In this case, accelerating HPC applications with FPGAs is similar to that of porting uniprocessor applications to massively parallel processors, with two key distinctions:• FPGAs are far more different from uniprocessors than MPPs are from uniprocessors, and• the process of parallelizing code for MPPs, while challenging, is still better understood and supported than porting codes to FPGAs.Lawrence Snyder stated the three basic parameters for the MPP portability problem. 3 First, a parallel solution using P processors can improve the best sequential solution by a factor of P, at most. Second, HPC problems tend to have third-or fourth-order complexity, and so parallel computation, while essential, offers only modest benefits. Third, "the whole force of parallelism must be transferred to the problem, not converted to 'heat' of implementational overhead."Researchers have addressed the portability problem periodically over the past 30 years, with well-known approaches involving language design, optimizing compilers, emulation, software engineering tools and methods, and function and application libraries. It is generally agreed that compromises are required: Either restrict the variety of architectures or scope of application, or bound expectations of performance or ease of implementation.

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Chapter 2 Elements of High‐Performance Reconfigurable Computing

VanCourt

Herbordt

2009

Advances in Computers

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Sizing of Processing Arrays for FPGA-Based Computation

Cited by 6 publications

References 16 publications

Architecture model for approximate tandem repeat detection

Architecture model for approximate tandem repeat detection

Achieving High Performance with FPGA-Based Computing

Chapter 2 Elements of High‐Performance Reconfigurable Computing

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