2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) 2016
DOI: 10.1109/eosesd.2016.7592563
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From quasi-static to transient system level ESD simulation: Extraction of turn-on elements

Abstract: Transient simulation is a main challenge to achieve system level ESD failure prediction. During the turn-on of the protections, complex phenomena introduce complex transient behaviors. In this paper we investigate the parameters that have to be added to perform accurate transient simulations and we propose a methodology to extract them by measurements.

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Cited by 11 publications
(9 citation statements)
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“…Building accurate models for system level ESD is not an easy task [2]. One of the most related problem is to have correct models that take into account the dynamic behavior, such as the protection device's triggering behavior to obtain a good estimation of the over-voltages [3] [4].…”
Section: Introductionmentioning
confidence: 99%
“…Building accurate models for system level ESD is not an easy task [2]. One of the most related problem is to have correct models that take into account the dynamic behavior, such as the protection device's triggering behavior to obtain a good estimation of the over-voltages [3] [4].…”
Section: Introductionmentioning
confidence: 99%
“…There are several LIN component manufacturers, we choose three of them named A, B and C. We know that each manufacturer has its own IC's protection strategy that is studied in the first part using the SEED methodology [1]. Based on [2], two kinds of failure can be studied, the first one called "hard failure", is the destruction of the IC, already mentioned in [3] [4]. We are now focusing on the "Soft Failure" [5] [6] [7] [8] which relates to functional problems such as the lost of clock, RESET, etc… In our study, we focus on communication problem that induced the loose of information on the LIN, due to an EFT event.…”
Section: Introductionmentioning
confidence: 99%
“…The same pattern to inject a stress and to measure is placed both on the LIN input and the Vbat pin. This pattern allows us to have a local monitoring, but also to add some external components as described in [2]. To inject the stress a diode is used on this injection pattern (between the TLP injection and LIN pin on Fig.…”
Section: Introductionmentioning
confidence: 99%
“…Following previous works [3,5,9], behavioral models of the on-chip protection strategy are built using quasi-static measurements. We extract the quasistatic IV curves of the LIN components using a TLP generator with 100ns duration and 1ns rise time.…”
Section: Esd Protection Blockmentioning
confidence: 99%
“…The i(t) signal representing the current through the device is transfered to the Failure Block to compute the failure level. As the determination of the failure is based on the current shape, a precise dynamic protection model is built following the methodology described in [9] where the dynamic behavior of the protection is externally measured.…”
Section: Esd Protection Blockmentioning
confidence: 99%