From Reconfigurable Architectures to Self-Adaptive Autonomic Systems

Santambrogio, Marco D.

doi:10.1109/cse.2009.490

Cited by 16 publications

(5 citation statements)

References 28 publications

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“…An autonomic manager is a feedback control loop that collects details from the system and acts accordingly based on the knowledge it has about the managed system. Autonomic Computing has stemmed essentially from distributed and Cloud systems, but is also sometimes considered in reconfigurable hardware architectures [2] as is the case in our present work.…”

Section: B Autonomic Computingmentioning

confidence: 99%

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A Domain-Specific Language for Autonomic Managers in FPGA Reconfigurable Architectures

Gueye

Delaval

Rutten

et al. 2018

2018 IEEE International Conference on Autonomic Computing (ICAC)

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Field Programmable Gate Array (FPGA) architectures are suitable hardware platforms for systems that need high performance and flexibility, because they support dynamic partial reconfiguration (DPR) to implement adaptive hardware algorithms e.g., for performance or energy efficiency. They are used for example in embedded systems such as UAV, e.g. for video processing. It is a challenge to design Autonomic Managers for such highly dynamic systems, taking into account the combinatorial design space of configurations and criteria and policies to decide on whether to reconfigure, and what next configuration to choose. In this paper, we propose a Domain Specific Language (DSL) called Ctrl-DPR, allowing designers to easily generate Autonomic Managers. They can describe their system and their management strategies, in terms of the entities composing the system : tasks, versions, applications, ressources, policies. The DSL relies on a behavioural modelling of these entities, targeted at the design of autonomic managers to control the reconfigurations in such a way as to enforce given policies and strategies. The models we use involve automata to describe the state space of configurations, and the transitions representing reconfigurations; they also involve discrete control techniques exploiting such models in order to obtain a correct runtime manager. These model-based control techniques are embedded in a compiler, connected to a reactive language and discrete controller synthesis tool, which enables to generate a C implementation of the controller enforcing the management strategies. We apply our DSL for the management of a video application on a UAV.

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Section: B Autonomic Computingmentioning

confidence: 99%

“…This management can be automated by control loops as addressed in Autonomic Computing [1]. Autonomic Computing has stemmed from distributed and Cloud systems, but is also sometimes considered in reconfigurable hardware architectures [2] as is the case in our present work.…”

Section: Introductionmentioning

confidence: 97%

A Domain-Specific Language for Autonomic Managers in FPGA Reconfigurable Architectures

Gueye

Delaval

Rutten

et al. 2018

2018 IEEE International Conference on Autonomic Computing (ICAC)

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“…This approach is exploring amongst others the application of Control Theory to design the feedback controllers themselves. Most of the state of the art concerns software systems, but some works also consider reconfigurable hardware [14].…”

Section: A Dynamic Partial Reconfigurable Fpgamentioning

confidence: 99%

Discrete and Logico-Numerical Control for Dynamic Partial Reconfigurable FPGA-Based Embedded Systems: A Case Study

Gueye

Delaval

Rutten

et al. 2018

2018 IEEE Conference on Control Technology and Applications (CCTA)

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Embedded systems need to be more and more self-adaptive, in order to better manage their constrained resources, and to better take into account evolutions in their environment and in their computing architecture. They can benefit from Field Programmable Gate Array (FPGA) architectures , which supports Dynamic Partial Reconfiguration (DPR) of the running fonctions, enabling improved performance and power consumption. The reconfigurations need to be decided and controlled in a closed loop. We approach this problem by applying techniques from the area of Supervisory Control for Discrete Event Systems (DES), where the space of configurations at the different levels (application, tasks, hardware platform) are modeled with automata, using the tools Heptagon/BZR and ReaX. This paper contributes with (i) generic modeling of the behaviors and objectives ; (ii) applications of Discrete Controller Synthesis (DCS), especially logico-numerical control ; (iii) concrete implementation on a FPGA hardware platform for an embedded video processing case study.

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“…Within this context classical reconfigurable and multicore systems are moving to self-aware computing systems [29] where hardware components [7,[30][31][32], the applications [33,34] and the operating system [26] can be made to autonomously adapt their behavior to achieve the best performance.…”

Section: An Overview Of Self-aware Systemsmentioning

confidence: 99%

Enabling technologies for self-aware adaptive systems

Santambrogio

Hoffmann

Eastep

et al. 2010

2010 NASA/ESA Conference on Adaptive Hardware and Systems

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Self-aware computer systems will be capable of adapting their behavior and resources thousands of times a second to automatically find the best way to accomplish a given goal despite changing environmental conditions and demands. Such a capability benefits a broad spectrum of computer systems from embedded systems to supercomputers and is particularly useful for meeting power, performance, and resource-metering challenges in mobile computing, cloud computing, multicore computing, adaptive and dynamic compilation environments, and parallel operating systems. Some of the challenges in implementing self-aware systems are a) knowing within the system what the goals of applications are and if they are meeting them, b) deciding what actions to take to help applications meet their goals, and c) developing standard techniques that generalize and can be applied to a broad range of self-aware systems. This work presents our vision for self-aware adaptive systems and proposes enabling technologies to address these three challenges. We describe a framework called Application Heartbeats that provides a general, standardized way for applications to monitor their performance and make that information available to external observers. Then, through a study of a self-optimizing synchronization library called Smartlocks, we demonstrate a powerful technique that systems can use to determine which optimization actions to take. We show that Heartbeats can be applied naturally in the context of reinforcement learning optimization strategies as a reward signal and that, using such a strategy, Smartlocks are able to significantly improve performance of applications on an important emerging class of multicore systems called asymmetric multicores.

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From Reconfigurable Architectures to Self-Adaptive Autonomic Systems

Cited by 16 publications

References 28 publications

A Domain-Specific Language for Autonomic Managers in FPGA Reconfigurable Architectures

A Domain-Specific Language for Autonomic Managers in FPGA Reconfigurable Architectures

Discrete and Logico-Numerical Control for Dynamic Partial Reconfigurable FPGA-Based Embedded Systems: A Case Study

Enabling technologies for self-aware adaptive systems

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