From signal temporal logic to FPGA monitors

Jakšić, Stefan; Bartocci, Ezio; Grosu, Radu; Kloibhofer, Reinhard; Nguyen, Thang; Nickovie, Dejan

doi:10.1109/memcod.2015.7340489

Cited by 45 publications

(20 citation statements)

References 19 publications

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“…Ideally, a single method would have been used, but both approaches were used by different teams in the competition. Monitoring hardware In the last decade, the increasing complexity of the circuit design has been making their verification and validation more convenient to perform using hardware emulation instead of the classical simulation, a task becoming very time consuming and expensive for the industry [57,72].…”

Section: Lessons Learned and Discussionmentioning

confidence: 99%

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First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

Bartocci

Falcone

Bonakdarpour

et al. 2017

Int J Softw Tools Technol Transfer

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The first international Competition on Runtime Verification (CRV) was held in September 2014, in Toronto, Canada, as a satellite event of the 14th international conference on Runtime Verification (RV'14). The event was organized in three tracks: (1) offline monitoring, (2) online monitoring of C programs, and (3) online monitoring of Java programs. In this paper, we report on the phases and rules, a description of the participating teams and their submitted benchmark, the (full) results, as well as the lessons learned from the competition.

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Section: Lessons Learned and Discussionmentioning

confidence: 99%

“…FoCs [35] developed by IBM and MBAC [25][26][27] [57,58,72,79] propose several practical techniques for generating FieldProgrammable Gate Array (FPGA) hardware monitors for Signal Temporal Logic (STL), an extension of MTL handling predicates over the real-values.…”

Section: Lessons Learned and Discussionmentioning

confidence: 99%

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

Bartocci

Falcone

Bonakdarpour

et al. 2017

Int J Softw Tools Technol Transfer

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“…SI consists in adding extra code to track the execution of particular software components and to output an execution trace that can be monitored. The two main approaches for software instrumentation are performed either at the source code level [36,136,105,10,138,121] or at the binary level [34,40,114,119,108]. Furthermore, SI can be static or dynamic whether they occur before (i.e., compilation-/link-time) or at execution time (i.e., tracking dynamically linked libraries).…”

Section: Software Instrumentationmentioning

confidence: 99%

Introduction to Runtime Verification

Bartocci

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Francalanza

et al. 2018

Lecture Notes in Computer Science

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209

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Abstract. The aim of this chapter is to act as a primer for those wanting to learn about Runtime Verification (RV). We start by providing an overview of the main specification languages used for RV. We then introduce the standard terminology necessary to describe the monitoring problem, covering the pragmatic issues of monitoring and instrumentation, and discussing extensively the monitorability problem.

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“…Inspired by these constructions, an optimized approach for bounded future properties was presented in [19]. Hardware runtime monitors for realtime properties were presented by Jaksic et al [24], where monitors for STL specifications were implemented in an FPGA. Further work on FPGA implementations of real-time temporal specification was introduced with the tool R2U2 [34,35], an outline monitoring approach that allows for monitoring specifications in MTL including future-time specifications.…”

Section: Related Workmentioning

confidence: 99%

FPGA Stream-Monitoring of Real-time Properties

Baumeister

Finkbeiner

Schwenger

et al. 2019

ACM Trans. Embed. Comput. Syst.

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An essential part of cyber-physical systems is the online evaluation of real-time data streams. Especially in systems that are intrinsically safety-critical, a dedicated monitoring component inspecting data streams to detect problems at runtime greatly increases the confidence in a safe execution. Such a monitor needs to be based on a specification language capable of expressing complex, highlevel properties using only the accessible low-level signals. Moreover, tight constraints on computational resources exacerbate the requirements on the monitor. us, several existing approaches to monitoring are not applicable due to their dependence on an operating system.We present an FPGA-based monitoring approach by compiling an RTL specification into synthesizable VHDL code. RTL is a stream-based specification language capable of expressing complex real-time properties while providing an upper bound on the execution time and memory requirements. e statically determined memory bound allows for a compilation to an FPGA with a fixed size. An advantage of FPGAs is a simple integration process in existing systems and superb executing time. e compilation results in a highly parallel implementation thanks to the modular nature of RTL specifications. is further increases the maximal event rate the monitor can handle.

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From signal temporal logic to FPGA monitors

Cited by 45 publications

References 19 publications

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

First international Competition on Runtime Verification: rules, benchmarks, tools, and final results of CRV 2014

Introduction to Runtime Verification

FPGA Stream-Monitoring of Real-time Properties

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