From software to accelerators with LegUp high-level synthesis

Canis, Andrew; Choi, Jongsok; Fort, Blair; Lian, Ruolong; Huang, Qijing; Calagar, Nazanin; Gort, Marcel; Qin, Jia Jun; Czajkowski, Tomasz; Brown, Stephen D.; Anderson, Jason

doi:10.1109/cases.2013.6662524

Cited by 39 publications

(16 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Although our work will apply to any FPGA which provides dynamic power control, and any high-level synthesis tool, we describe it in the context of the Dynamic Power-Gated FPGA architecture from [1] and the LegUp high-level synthesis tool from [10]. In this section, we present background about each.…”

Section: Contextmentioning

confidence: 99%

“…Our work is based on LegUp: A high-level open source synthesis framework [10]. LegUp automatically generates an SoC consisting of a MIPS processor and one or more accelerators from an application design expressed in C. The application is first profiled on a hardware profiler to identify the functions that would benefit from hardware implementation.…”

Section: B Legup High-level Synthesis Frameworkmentioning

confidence: 99%

“…In particular, we focus on SoC designs that are created using a High-Level Synthesis (HLS) methodology, and identify opportunities during HLS. A typical SoC design created using an HLS methodology, such as [10], contains a processor with one or more hardware accelerators used to speed up critical portions of the algorithm. We consider power gating at the accelerator-level as it is wellsuited as a unit of granularity for power-gating architectures such as the one in [1].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

Ahmed

Bsoul

Wilton

et al. 2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

Static leakage power consumption is critical in modern FPGAs for many applications. Dynamic Power-Gating (DPG), in which parts of the FPGA in-use logic blocks are powered-down at run-time, is a promising technique to reduce the static power. Adoption of such emerging DPG enabled FPGA architectures remains challenging as the current toolchains to program the FPGA does not support this type of power-gating. Moreover, manually identifying profitable powergating opportunities in an application requires significant design expertise and is time consuming. In this paper, we propose a high-level synthesis-based design framework that exploits the dynamic power-gating feature of the FPGAs to minimize the static power dissipation. We use this framework on a set of CHStone benchmark suite and demonstrate that power-gating opportunities for hardware accelerators can be identified in an automatic way. Results show that up to 96% reduction in static energy is achieved for individual accelerators using dynamic power-gating technique.

show abstract

Section: Contextmentioning

confidence: 99%

Section: B Legup High-level Synthesis Frameworkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

Ahmed

Bsoul

Wilton

et al. 2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

show abstract

“…There are also other HLS-based software simulators. The LegUp HLS [2] simulator provides speedup prediction based on the profiling of the source code and the execution cycle from its synthesis result. HLScope+ [6] describes a method to extract cycle information that is hidden by HLS abstraction and uses Vivado HLS C simulation to predict the performance for applications with dynamic behavior.…”

Section: Related Workmentioning

confidence: 99%

Rapid Cycle-Accurate Simulator for High-Level Synthesis

Chi

Choi

Cong

et al. 2019

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

View full text Add to dashboard Cite

A large semantic gap between the high-level synthesis (HLS) design and the low-level (on-board or RTL) simulation environment often creates a barrier for those who are not FPGA experts. Moreover, such low-level simulation takes a long time to complete. Softwarebased HLS simulators can help bridge this gap and accelerate the simulation process; however, we found that the current FPGA HLS commercial software simulators sometimes produce incorrect results. In order to solve this correctness issue while maintaining the high speed of a software-based simulator, this paper proposes a new HLS simulation flow named FLASH. The main idea behind the proposed flow is to extract the scheduling information from the HLS tool and automatically construct an equivalent cycle-accurate simulation model while preserving C semantics. Experimental results show that FLASH runs three orders of magnitude faster than the RTL simulation.

show abstract

“…The impact of various LLVM optimizations on the performance of the generated hardware structures is explored in [41]. Extra passes are added to LLVM for HLS and work in three phases: allocation, scheduling, and binding.…”

Section: Legup 30 (U Toronto)mentioning

confidence: 99%

High-Level Language Tools for Reconfigurable Computing

Windh

Halstead

et al. 2015

Proc. IEEE

View full text Add to dashboard Cite

| In the past decade or so we have witnessed a steadily increasing interest in FPGAs as hardware accelerators:they provide an excellent mid-point between the reprogrammability of software devices (CPUs, DSPs, and GPUs) and the performance and low energy consumption of ASICs. However, the programmability of FPGA-based accelerators remains one of the biggest obstacles to their wider adoption. Developing FPGA programs requires extensive familiarity with hardware design and experience with a tedious and complex tool chain.

show abstract

From software to accelerators with LegUp high-level synthesis

Cited by 39 publications

References 20 publications

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

Rapid Cycle-Accurate Simulator for High-Level Synthesis

High-Level Language Tools for Reconfigurable Computing

Contact Info

Product

Resources

About