FSM-Based Logic Controller Synthesis in Programmable Devices with Embedded Memory Blocks

Borowik, Grzegorz; Łabiak, Grzegorz; Bukowiec, Arkadiusz

doi:10.1007/978-3-319-12652-4_8

Cited by 5 publications

(3 citation statements)

References 25 publications

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“…Functionally complete sets of logical operations containing only one operation are the Schaeffer basis, which includes the Schaeffer stroke function "| ", and the Webb (Pierce) basis, which includes the Pierce arrow function "↓" [24][25][26].…”

Section: Methodsmentioning

confidence: 99%

Information and logical transformations in Schaeffer and Pierce Bases in Maple

Olenev,

Potekhina,

Khabarov

et al. 2024

ITM Web Conf.

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One of the tasks of synthesis and analysis of the functioning of combinational devices is the representation of a Boolean function in various bases. The absolute completeness of the use and implementation of various transformations of Boolean functions is impossible without the implementation of transformations into universal bases of Schaeffer (AND-NOT) or Webb (OR-NOT). The Logic library of the Maple computer algebra system allows you to use only the operations &nand (Schaeffer basis) and &nor (Webb basis) to build a model of a digital device. Therefore, there is a need to expand the functionality of the Logic library of the Maple computer algebra system by representing Boolean functions in Schaeffer and/or Pierce (Webb) bases. In this regard, the authors of the article have developed procedures that allow the representation of disjunctive or conjunctive normal forms in the Schaeffer basis or in the Webb basis. The development was carried out taking into account the existing data processing functions and procedures. The article describes the technology of extending the Logic library of the Maple computer algebra system by developed procedures that implement the transformation of a given or received Boolean function in Schaeffer or Webb bases.

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Section: Methodsmentioning

confidence: 99%

Information and logical transformations in Schaeffer and Pierce Bases in Maple

Olenev,

Potekhina,

Khabarov

et al. 2024

ITM Web Conf.

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“…Such mapping is trivial in a case of two-level minimization in a form of DNF or CNF. However, FPGA circuits feature a multilevel implementation of Boolean functions [6][7][8][9]. Optimal conversion of a multilevel circuit from the {AND, OR, NOT} basis to the {NOR, NAND} basis is an uneasy task.…”

Section: Fig 1 Implementation Of the Elements Of The Basic Basis {Nmentioning

confidence: 99%

Implementation of the method of image transformations for minimizing the Sheffer functions

Solomko¹,

Хомюк²,

Ivashchuk³

et al. 2020

EEJET

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The studies have established the possibility of reducing computational complexity, higher productivity of minimization of the Boolean functions in the class of expanded normal forms of the Sheffer algebra functions by the method of image transformations. Expansion of the method of image transformations to the minimization of functions of the Sheffer algebra makes it possible to identify new algebraic rules of logical transformations. Simplification of the Sheffer functions on binary structures of the 2-(n, b)-designs features exceptional situations. They are used both when deriving the result of simplification of functions from a binary matrix and introducing the Sheffer function to the matrix. It was shown that the expanded normal form of the n-digit Sheffer function can be represented by binary sets or a matrix. Logical operations with the matrix structure provide the result of simplification of the Sheffer functions. This makes it possible to concentrate the principle of minimization within the truth table of a given function and do without auxiliary objects, such as Karnaugh map, Weich diagrams, coverage tables, etc. Compared with the analogs of minimizing the Sheffer algebra functions, the method under the study makes the following to be possible:-reduce algorithmic complexity of minimizing expanded normal forms of the Sheffer functions (ENSF-1 and ENSF-2);-increase the productivity of minimizing the Sheffer algebra functions by 100-150 %;-demonstrate clarity of the process of mi nimizing the ENSF-1 or ENSF-2;-ensure self-sufficiency of the method of image transformations to minimize the Sheffer algebra functions by introducing the tag of mini mum function and minimization in the complete truth table of the ENSF-1 and ENSF-2. There are reasons to assert that application of the method of image transformations to the minimization of the Sheffer algebra functions brings the problem of minimization of the ENSF-1 and ENSF-2 to the level of a wellstudied problem in the class of disjunctiveconjunctive normal forms (DCNF) of Boolean functions

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“…It is usual that designers try to use FPGA resources for a different purpose than for which they were included. Following the principle called "use it or lose it", different works in the literature have proposed an unconventional use of FPGA resources; a typical example is the use of embedded memory blocks to implement finite state machines [4][5][6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

Senhadji-Navarro

García-Vargas

2021

Electronics

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Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non-arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.

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FSM-Based Logic Controller Synthesis in Programmable Devices with Embedded Memory Blocks

Cited by 5 publications

References 25 publications

Information and logical transformations in Schaeffer and Pierce Bases in Maple

Information and logical transformations in Schaeffer and Pierce Bases in Maple

Implementation of the method of image transformations for minimizing the Sheffer functions

Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

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