Full-chip pitch/pattern splitting for lithography and spacer double patterning technologies

Chiou, Tsann-Bim; Socha, Robert; Kang, Houyang; Chen, Alek C.; Hsu, Stephen; Chen, Hong; Chen, Luoqi

doi:10.1117/12.804763

Cited by 12 publications

(7 citation statements)

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“…M2 overlay error to -3σ that leads to smaller space between M2 segment and its neighbor results to maximum 13% increase of crosstalk-induced delay, and M2 +3σ width increase that also leads to smaller space with a neighbor net shows maximum 16% of crosstalk-induced delay. Unlike the two parallel line case of M2 segment, M4 width variation affects maximum 23% which comes from the coupling increase of both sides, but M4 overlay error has 6 Impact of M1 coloring and overlay error are included in cell characterization, so M1 can be excluded in circuit level DOE. 7 Metal density is calculated from only signal nets.…”

Section: Full-chip Analysis Setupmentioning

confidence: 99%

“…We assume 20% of M1 design rules as 3σ variation of overlay error and width, i.e., 10.4nm for each. 6 We implement the AES core, obtained as RTL from the opensource site opencores.org [26]. With 4ns clock cycle time, we perform synthesis, placement and routing with NanGate 45nm OpenLibrary [25] using Cadence RTL Compiler v5.2 [30] and Cadence SOC Encounter v7.2 [32].…”

Section: Full-chip Analysis Setupmentioning

confidence: 99%

“…SDP is seen as a very viable option for regular patterns such as poly gates [4] as well as bitlines [5] of a memory design. However, SDP requires additional process steps, including chemical-mechanical polishing which may be costly and difficult to optimize, and also requires a trim mask to remove undesired spacer (trimming) or generated patterns (repairing) when implementing irregular patterns [4], [6].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Kahng¹,

Li²,

Peh³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

563

338

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Double patterning lithography seems to be a prominent choice for 32nm and 22nm technologies. Double patterning lithography techniques require additional masks for a single interconnect layer. Consequently, mask shift-induced overlay errors introduce additional variability into interconnect coupling capacitances. An important open question is whether overlay-induced performance impacts are more significant than performance variations caused by variability in interconnects. We provide TCAD as well as chip-level analyses to determine whether overlay error should receive more attention than interconnect variations during interconnect manufacturing. We develop conclusions to help determine which component should be given more importance in specific double patterning process variants.

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Section: Full-chip Analysis Setupmentioning

confidence: 99%

Section: Full-chip Analysis Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Kahng¹,

Li²,

Peh³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

563

338

View full text Add to dashboard Cite

show abstract

“…It consists of an inexpensive and non-critical trim-exposure cycle (resist coat-expose-develop) and removal of hardmask corresponding to extra printed features before the final etch. The trim exposure is a mature and well-known method used in many patterning techniques such as SADP [9,10], alternating phase-shift mask [11], and subtractive-litho patterning [12,13]. It was recently employed to trim-away printing assist features (PrAF) introduced to enhance the resolution of conventional single patterning [14].…”

Section: A Manufacturing Processmentioning

confidence: 99%

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Ghaida

Torres

Gupta

2011

IEEE Trans. Semicond. Manufact.

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Abstract-1 We propose shift-trim double patterning lithography (ST-DPL), a cost-effective double patterning technique for achieving pitch relaxation with a single photomask. The mask is re-used for the second exposure by applying a translational mask-shift. An additional non-critical trim exposure is applied to remove extra printed features. ST-DPL can be used to pattern critical layers and is very suitable for regular and gridded layouts, where redesign effort and area overhead are minimal. In this paper, the viability of ST-DPL is demonstrated through a design implementation at the poly and contacts layers in bidirectional layouts. Standard-cell layouts are constructed so as to avoid layout decomposition conflicts, which are found to be the limiting factor for the pitch relaxation that can be achieved with double-patterning (ST-DPL as well as standard DPL). 2× pitch relaxation being associated with a considerable area overhead, 1.8× pitch relaxation is achieved in our implementation while ensuring no layout decomposition conflicts and a small area overhead. Specifically, in comparison to layouts assumed to be feasible with a hypothetical single-patterning process, we observe virtually no area overhead when ST-DPL is applied to the poly layer (<0.3% cell-area overhead) and no more than 4.7% cellarea overhead when ST-DPL is applied at both the poly and contacts layers. The proposed method has many benefits over standard pitch-split double-patterning: (1) cuts mask-cost to nearly half, (2) reduces overlay errors between the two patterns, (3) alleviates the bimodal line-width distribution problem in double patterning, and (4) slightly enhances the throughput of critical-layer scanners.

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“…Trim-exposure is a mature and well-known method used in many patterning techniques such as double-patterning with spacer [14,15], alternating phase-shift mask [13], and subtractive-litho patterning [17,18]. It was recently employed to trim-away printing assist features (PrAF) introduced to enhance the resolution of conventional single patterning [16].…”

Section: Manufacturing Processmentioning

confidence: 99%

Single-mask double-patterning lithography

2009

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This paper proposes shift-trim double patterning lithography (ST-DPL), a cost-effective method for achieving 2× pitchrelaxation with a single photomask (especially at polysilicon layer). The mask is re-used for the second exposure by applying a translational mask-shift. Extra printed features are then removed using a non-critical trim exposure. The viability of ST-DPL is demonstrated. The proposed method has many advantages with virtually no area overhead (< 0.3% standard-cell area): (1) cuts mask-cost to nearly half that of standard-DPL, (2) reduces overlay errors between the two patterns and can virtually eliminate it in some process implementations, (3) alleviates the bimodal problem in doublepatterning, and (4) enhances throughput of first-rate scanners. We implement a small 45nm standard-cell library and small benchmark designs with ST-DPL to illustrate its viability.

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Full-chip pitch/pattern splitting for lithography and spacer double patterning technologies

Cited by 12 publications

References 0 publications

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration

Single-Mask Double-Patterning Lithography for Reduced Cost and Improved Overlay Control

Single-mask double-patterning lithography

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