Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling

Bellaouar, A.; Abu-Khater, Issam S.; Elmasry, M.I.; Chikima, A.

doi:10.1109/4.293115

Cited by 7 publications

(1 citation statement)

References 13 publications

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“…In the proposed new logic circuits, the true-single-phase clocking (TSPC) scheme is used so that the clock driving and distribution are simple and less chip area is occupied by clock lines [10]- [19]. Furthermore, the bootstrapping technique [4], [9], [20], [21] is used to obtain fast operation and nearfull-swing output. It is shown that under 2-V operation, the new BiCMOS dynamic logic circuits and latch logic circuits, as well as the formed new pipelined logic circuits, have better speed performance than both conventional BiCMOS and CMOS design.…”

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confidence: 99%

A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications

Tseng

1999

IEEE J. Solid-State Circuits

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New true-single-phase-clocking (TSPC) BiCMOS/ BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1-m BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clockhigh-evaluate-BiCMOS dynamic latch logic circuit and clock-lowevaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1-m BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications. Index Terms-BiCMOS pipelined system, low-voltage BiCMOS dynamic logic circuits, true single-phase clocking (TSPC). I. INTRODUCTION B iCMOS technology has been widely applied to the design of memories and high-performance very-large-scale integrated circuit (VLSI) logic due to its advantageous features of high speed, high driving capability, and low power dissipation [1]. In the design of conventional BiCMOS static logic circuits, extra PMOS devices should be used with NMOS devices to realize logic functions. As a consequence, the chip area is large, especially in complex logic. Also, both power dissipation and speed performance are degraded.

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confidence: 99%