Full System Simulation of Optically Interconnected Chip Multiprocessors Using gem5

Laer, Anouk Van; Jones, Timothy M.; Watts, Philip M.

doi:10.1364/ofc.2013.oth1a.2

Cited by 7 publications

(3 citation statements)

References 12 publications

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“…The ring resonators are sized for switching a wavelength striped message of 16 wavelengths of 10 Gb/s per wavelength to reduce serialisation latency. This bandwidth was previously shown to be optimal in full system gem5 simulations of PARSEC benchmarks .…”

Section: System Parameters and Assumptionsmentioning

confidence: 90%

Towards zero latency photonic switching in shared memory networks

Madarbux

Laer

Watts

et al. 2014

Concurrency and Computation

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Optical networks on chip based on silicon photonics have been proposed to reduce latency and power consumption in future chip multiprocessors. However, high performance chip multiprocessors use a shared memory model, which generates large numbers of short messages, creating high arbitration latency overhead for photonic switching networks. In this paper, we explore techniques that intelligently use information from the memory hierarchy to predict communication in order to setup photonic circuits with reduced or eliminated arbitration latency. Firstly, we present a switch scheduling algorithm, which arbitrates on a per memory transaction basis and holds open photonic circuits to exploit temporal locality. We show that this can reduce the average arbitration latency overhead by 60% and eliminate arbitration latency altogether for up to 70% of memory transactions. We then demonstrate that this switch scheduling algorithm operating with a central photonic crossbar or Clos switch has significant energy efficiency benefits over arbitrationfree photonic networks such as single writer multiple reader networks. Finally, we demonstrate that cache miss prediction can be used to predict 86% of more complex memory transactions involving multiple nodes or main memory.

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Section: System Parameters and Assumptionsmentioning

confidence: 90%

Towards zero latency photonic switching in shared memory networks

Madarbux

Laer

Watts

et al. 2014

Concurrency and Computation

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“…Other groups focus on integrating optical network models with the generic hardware system simulation, using SystemC [21], which allows functional verification as well as extended timing measurements. Models of optical networks have also been incorporated in the gem5 [22] and SESC [23] cycleaccurate simulators, allowing for application performance measurements. Although these efforts result in major advances in optical network understanding, they have their own fields and metrics of interest, and neglect other effects.…”

Section: Related Workmentioning

confidence: 99%

Modeling and simulation environment for photonic interconnection networks in high performance computing

Glick

Rumley

Hendry

et al. 2013

2013 15th International Conference on Transparent Optical Networks (ICTON)

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Computer network architects are concerned with reducing the execution time of applications while maintaining or reducing power consumption of the system. In order to demonstrate the advantages of photonic interconnection networks at the scale of high performance computer clusters and warehouse scale data centers, system level simulations are required. To achieve an appropriate level of accuracy both for device detail and system scale, a simulation suite, rather than a single simulation tool will be most efficient. We present our work on this topic and results for rack scale photonic interconnection networks for high performance computing. Keywords: optical networks, optical interconnects, simulation. INTRODUCTION AND MOTIVATIONSolutions are required to the newsworthy power consumption [3], latency [4] and bandwidth challenges [5] of high performance computing (HPC). Low latency, previously primarily viewed as a requirement for supercomputers, is becoming a more significant metric as the data center size increases to warehouse scale and web search results gather information from more servers [6,7]: beyond a given scale, the parallel efficiency (and thus the general efficiency) is directly related to the latency.Silicon photonics (SiP) [1,2] has the potential to address these challenges and offer improved network functionality. SiP based device capabilities and manufacturability are advancing rapidly in several key areas including: ring resonator temperature stabilization [8], integrated switch fabrics [9,10] and hybrid silicon technology [11]. Integrated silicon (and InP based) photonics reduce power consumption and cost in addition to providing high speed switching capabilities. With off chip bandwidths reaching 100's GB/s [12] high bandwidth photonics is clearly an option to reduce I/O bandwidth bottlenecks. However, proof of concept demonstrations at the device or link level are not sufficient to convince computer architects to incorporate photonics into their next generation system designs. On the other hand, system experiments from computer architects tend to focus on commercially available products, whose price and specifications can easily be obtained [1,2]. Enabling interaction between SiP device designers and computer architects is necessary for realizing novel systems with integrated silicon photonics. Consequently, we must take the extra steps to demonstrate, through modeling and simulations (and, where possible, test-bed validations), the effects of incorporating photonic technology in computer networks. This means, in addition to showing the impact on network metrics such as latency and bandwidth, developing tools that illustrate the execution time improvement of target applications.The optimal way to incorporate SiP into a large scale system depends on the communication requirements of the executed applications. We therefore need modeling and simulation tools to understand the interactions between real time applications and the hardware [24]. More specifically, we need to compare the various...

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“…To capture these dependencies, a network can be modeled within a cycle accurate simulation platform, such as gem5 [4] [24]. On these platforms, HPC sub-systems are described at the instruction set level.…”

Section: Related Workmentioning

confidence: 99%

A synthetic task model for HPC-grade optical network performance evaluation

Rumley

Pinals

Bergman

et al. 2013

Proceedings of the 3rd Workshop on Irregular Applications: Architectures and Algorithms

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With vastly increasing system parallelism, energy efficient data movement has emerged as one of the key challenges in High Performance Computing (HPC). Optics offers the potential for creating system-wide interconnection networks with extremely high bandwidth and energy efficiency. To reap the significant benefits of optical data movement, the interconnect design must go beyond a simple wire replacement to include a fully networked architecture. Simulation is an essential tool in the associated architecture design space exploration. However, simulation requires appropriate models for capturing the relevant interactions between parallel application communication and network operations, as well as the photonic physical layer integrity. An important goal is to keep the simulation as simple as possible to enable a wide design space exploration. In this paper, we propose a traffic generation model that captures the interactions and dependencies between computation and communication for a given application. Our proposed model remains tractable enough to be implemented on top of detailed photonic network simulators as well as general enough to analyze different components of the network under investigation.

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Full System Simulation of Optically Interconnected Chip Multiprocessors Using gem5

Abstract: By extending the cycle accurate gem5 computer system simulator with optical network models, we demonstrate chip multiprocessor performance improvements of up to 18% using a wavelength striped optical crossbar interconnect and determine optimum optical parameters.

Cited by 7 publications

References 12 publications

Towards zero latency photonic switching in shared memory networks

Towards zero latency photonic switching in shared memory networks

Modeling and simulation environment for photonic interconnection networks in high performance computing

A synthetic task model for HPC-grade optical network performance evaluation

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