2011
DOI: 10.1109/tns.2011.2169280
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Fully Automated, Testable Design of Fine-Grained Triple Mode Redundant Logic

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Cited by 12 publications
(5 citation statements)
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“…A cell library test chip [48] and the other test chips confirmed negligible I DD leakage increase (a few %) up to 2 Mrad(Si) [47] [46]. The caches have similar TID hardness, using annular NMOS transistors [40].…”
Section: Experimentally Measured Tid and Sel Hardnessmentioning
confidence: 79%
See 1 more Smart Citation
“…A cell library test chip [48] and the other test chips confirmed negligible I DD leakage increase (a few %) up to 2 Mrad(Si) [47] [46]. The caches have similar TID hardness, using annular NMOS transistors [40].…”
Section: Experimentally Measured Tid and Sel Hardnessmentioning
confidence: 79%
“…10 upper right). This allows an incorrect copy, whether brought into one of the D inputs or due to an SEU to be corrected in the low phase of the clock, when the slave feedback path is active [46]. The slave feedback is not in a critical timing path, so there is no impact on performance aside from the increased routing in TMR circuits.…”
Section: Tmr Self-correcting Flip-flopsmentioning
confidence: 99%
“…An important aspect of the rad-hard design with standard flip-flops is the compatibility with the design flow. Several previous approaches have proposed the modification of the design flow by introducing the processing of the synthesized design netlist, with the aim to convert the standard flip-flops into the TMR configurations [48]- [50]. Such an approach may be very exhaustive for a complex digital design with a large number of flip-flops.…”
Section: State-of-the-art Solutions For Rad-hard Flip-flopsmentioning
confidence: 99%
“…For the ASIC design of the hardened microprocessor HERMES [14], both DMR and TMR techniques were implemented, depending on which processor block was to be hardened, and the replicated redundancy domains were physically separated during the circuit layout design phase. Another approach in fine-grain techniques is the one proposed on [15], in which design flip-flops are replaced by self-correcting rad-hard by design (RHBD) flip-flops after synthesis, and triplication is performed on spatially separated regions during the placement phase. For FPGA designs, actions can be taken during the placement and routing implementation stages, such as inserting redundant routing connections [16] or using reliability-oriented place and route algorithms to physically separate the redundant copies and avoid single points of failure [17].…”
Section: Literature Surveymentioning
confidence: 99%