Fully Differential Ultra-Wideband Amplifier With 46 −dB Gain and Positive Feedback for Increased Bandwidth

An, Xin; Wagner, Jens; Ellinger, Frank

doi:10.1109/tcsii.2020.3032564

Cited by 4 publications

(6 citation statements)

References 10 publications

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“…In this case, the DC gain width product GBW, and slewrate SR+ and SR-are provided as: Figure 3 shows the amplifier macro model, where two sets of PWL g m (g mp , g mn ), input/output resistance (R ip , R in , R op , R on ), and input/output capacitance (C ip , C in , C op , C on ) are used to model the fully differential (FD) operation [16]. As such, g mp and g mn represents the input stage that is generally realized with differential pairs [17]. In addition, the input common mode (CM) level V I,CM is set by using the average of the two inputs V ip and V in .…”

Section: Amplifier Macro Modelmentioning

confidence: 99%

Macro Model for Discrete-Time Sigma‒Delta Modulators

Lee

2022

Electronics

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This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As such, since the macro model is a true representation of the actual transistor level circuit, a moderately good accuracy can be obtained. In addition, the proposed macro model includes the major amplifier, comparator, and switch‒capacitor non-idealities of the sigma‒delta modulator such as amplifier DC gain, GBW, slewrate, comparator bandwidth, hysteresis, parasitic capacitance, and switch-on resistance. The results show the simulation time of the proposed macro model sigma‒delta modulator is only 6.43% of the transistor level circuit with comparable accuracy. As a result, the proposed macro model can facilitate the circuit design and leverage non-ideality analysis of discrete-time sigma‒delta modulators. As a practical design example, a second order discrete-time sigma‒delta modulator with a five-level quantizer is realized using the propose macro model for GSM and WCDMA applications.

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Section: Amplifier Macro Modelmentioning

confidence: 99%

Macro Model for Discrete-Time Sigma‒Delta Modulators

Lee

2022

Electronics

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“…After simplification and guided by ref [16]; (6) Based on the derived formula of the GD presented in Eq.6 and circuit simulation at Fig. 9, Inductor L int has a great effect on the GD variation where increasing its value will improve the GD performance.…”

Section: Group Delaymentioning

confidence: 99%

“…In this standard, As seen in Fig. 1, the 3.1 -10.6 GHz spectrum is divided into low band of three channels (channels 0-2) and high band of eight channel (channels [3][4][5][6][7][8][9][10]. Each channel has a bandwidth of 499.2 MHz to achieve data rates for transmissions up to 480 Mb/s [4].…”

Section: Introductionmentioning

confidence: 99%

“…It is required for the UWB PAs to have broadband matching, flat gain over the desired bandwidth, good linearity, small group delay, and acceptable PAE. The CMOS UWB-PAs presented in literature adopt different topologies and operate over different bands such as 3.0 to 5.0 GHz, and 6.0 GHz to 10.0 GHz [6] - [25].…”

Section: Introductionmentioning

confidence: 99%

“…The resistive shunt feedback topology [6]- [8] achieves wideband matching and better gain flatness over wide bandwidth, but suffers from its small PAE and consumes large DC power consumption. Also, the distributed amplifiers provide a good wideband matching and broad gain-bandwidth.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

High Efficiency, Good phase linearity 0.18 µm CMOS Power Amplifier for MBAN-UWB Applications

Mosalam

Gad‐Allah

2021

Int. j. electr. comput. eng. syst. (Online)

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This paper presents the design of 3.1-10.6 GHz class AB power amplifier (PA) suitable for medical body area network (MBAN) Ultra-Wide Band (UWB) applications in TSMC 0.18 µm technology. An optimization technique to simultaneously maximize power added efficiency(PAE) and minimize group delay variation is employed. Source and Load-pull contours are used to design inter and output stage matching circuits. The post-layout simulation results indicated that the designed PA has a maximum PAE of 32 % and an output 1-dB compression of 11 dBm at 4 GHz. In addition, a small group delay variation of ± 50 ps was realized over the whole required frequency band . Moreover, the proposed PA has small signal power gain (S21) of 12.5 dB with ripple less than 1.5 dB over the frequency range between 3.1 GHz to 10.6 GHz, while consuming 36 mW.

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An Integrated Primary Impulse Radio Ultra-Wideband Radar for Short-Range Real-Time Localization

Wagner

Ellinger

2022

IEEE Trans. Circuits Syst. I

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Fully Differential Ultra-Wideband Amplifier With 46 −dB Gain and Positive Feedback for Increased Bandwidth

Cited by 4 publications

References 10 publications

Macro Model for Discrete-Time Sigma‒Delta Modulators

Macro Model for Discrete-Time Sigma‒Delta Modulators

High Efficiency, Good phase linearity 0.18 µm CMOS Power Amplifier for MBAN-UWB Applications

An Integrated Primary Impulse Radio Ultra-Wideband Radar for Short-Range Real-Time Localization

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