Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications

Long, Yu; Zhong, Tom; Hsu, W.N.; Kim, Sanghoek; Lu, Xiao; Kan, Jimmy J.; Park, C.; Chen, W. C.; Li, X.; Zhu, Xiwei; Wang, P.; Gottwald, Matthias; Fatehi, J.; Seward, Lee; Kim, J. P.; Yu, Nick; Jan, G.; Haq, Jesmin; Le, S.; Wang, Y. J.; Thomas, Luc; Zhu, Jian‐Gang; Liu, H.; Lee, Y. J.; Tong, Ru-Ying; Pi, K.; Shen, Dongna; He, Renren; Teng, Zhongjian; Lam, Vinh; Annapragada, Rao; Torng, Terry; Wang, Po-Kang; Kang, Sungwon

doi:10.1109/iedm.2015.7409770

Cited by 42 publications

(19 citation statements)

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“…Pipelining, however, requires complex circuitry. Logic in-memory architecture [35,36] In-memory logic for big-data applications Mitigates the bottleneck in data exchange between logic and memory Dual edge clocking [37] Reduces the clock frequency to half of the single edge-triggered flip-flops…”

Section: Gate Sizingmentioning

confidence: 99%

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Ogbebor

Imoize

Atayero

2020

Wireless Communications and Mobile Computing

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The projected rise in wireless communication traffic has necessitated the advancement of energy-efficient (EE) techniques for the design of wireless communication systems, given the high operating costs of conventional wireless cellular networks, and the scarcity of energy resources in low-power applications. The objective of this paper is to examine the paradigm shifts in EE approaches in recent times by reviewing traditional approaches to EE, analyzing recent trends, and identifying future challenges and opportunities. Considering the current energy concerns, nodes in emerging wireless networks range from limited-energy nodes (LENs) to high-energy nodes (HENs) with entirely different constraints in either case. In view of these extremes, this paper examines the principles behind energy-efficient wireless communication network design. We then present a broad taxonomy that tracks the areas of impact of these techniques in the network. We specifically discuss the preponderance of prediction-based energy-efficient techniques and their limits, and then discuss the trends in renewable energy supply systems for future networks. Finally, we recommend more context-specific energy-efficient research efforts and cross-vendor collaborations to push the frontiers of energy efficiency in the design of wireless communication networks.

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Section: Gate Sizingmentioning

confidence: 99%

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Ogbebor

Imoize

Atayero

2020

Wireless Communications and Mobile Computing

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“…Since these technologies are quite young and require further development, they are not considered in this work. On the contrary, several prototypes demonstrated the maturity of the STT-MRAM technology ( [7], [8], [9], [10]). …”

Section: Introductionmentioning

confidence: 99%

Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable Devices

et al. 2017

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Since the advent of complementary metal oxide semiconductors (CMOS), the number of transistor per die never stops increasing to reach today several billion of transistors. As a result, design and fabrication of smart devices able to run at high speed has been possible. However, the power consumption of systems-on-chip has significantly increased due to the high density integration and the high leakage power of current CMOS transistors. As a result, a heat dissipation wall makes difficult further improvement in performance. Having high autonomy for battery-powered devices becomes a real challenge. To deal with these issues, STT-MRAM technology is seen as a promising solution. In addition to its attractive performance features, STT-MRAM can bring non-volatility inside a system to allow full data retention after a complete shutdown while keeping a fast wake-up time. Considering two 32-bit embedded processors, this paper shows how STT-MRAM can improve energy efficiency and reliability of future embedded systems thanks to normally-off computing and checkpointing/rollback techniques. Finally, a detailed analysis is performed to evaluate the cost related to the backup/recovery of the system. Index Terms-Spintronic memory and logic, embedded processor.

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“…Resistive memories [1], [2] are a class of non-volatile embedded memories that have the potential to be a universal memory technology by providing the density of DRAM, the speed of SRAM and the non-volatility of Flash. Resistive memories typically consist of a 1T-1R structure [3], [4], with a resistive storage device (e.g.…”

Section: Introductionmentioning

confidence: 99%

An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS

Biswas

Arslan

Hamzaoglu

et al. 2017

2017 IEEE Custom Integrated Circuits Conference (CICC)

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This paper presents a low-offset read sensing scheme for resistive memories. Due to increasing device variations in sub-32 nm CMOS processes, it becomes very challenging to design a high yield and low-offset read-sensing scheme. In this work we address these issues by using a pseudo-differential sensing scheme to get 2× signal margin and by full offset cancellation of the sense-amplifier, making it more suitable to tolerate variation from the memory array due to storage device resistance variation. Measurement results show the sense-amplifier can work with a 20mV input, which makes it ideal for small-signal sensing for resistive memories.

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Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications

Cited by 42 publications

References 1 publication

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions

Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable Devices

An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOS

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