Functional Debug Techniques for Embedded Systems

Vermeulen, Bart

doi:10.1109/mdt.2008.66

Cited by 43 publications

(20 citation statements)

References 11 publications

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“…A fault-locating method exists that works by connecting a debugger externally to the ECU [14]. This involves connecting the debugger to debugging pins on the outside of the ECU and monitoring the memory state during program execution, as in the joint test action group (JTAG) background debug mode (BDM).…”

Section: Testing and Debugging In A Black-box Environmentmentioning

confidence: 99%

Fault Localization Method by Partitioning Memory Using Memory Map and the Stack for Automotive ECU Software Testing

2016

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Abstract:Recently, the usage of the automotive Electronic Control Unit (ECU) and its software in cars is increasing. Therefore, as the functional complexity of such software increases, so does the likelihood of software-related faults. Therefore, it is important to ensure the reliability of ECU software in order to ensure automobile safety. For this reason, systematic testing methods are required that can guarantee software quality. However, it is difficult to locate a fault during testing with the current ECU development system because a tester performs the black-box testing using a Hardware-in-the-Loop (HiL) simulator. Consequently, developers consume a large amount of money and time for debugging because they perform debugging without any information about the location of the fault. In this paper, we propose a method for localizing the fault utilizing memory information during black-box testing. This is likely to be of use to developers who debug automotive software. In order to observe whether symbols stored in the memory have been updated, the memory is partitioned by a memory map and the stack, thus the fault candidate region is reduced. A memory map method has the advantage of being able to finely partition the memory, and the stack method can partition the memory without a memory map. We validated these methods by applying these to HiL testing of the ECU for a body control system. The preliminary results indicate that a memory map and the stack reduce the possible fault locations to 22% and 19% of the updated memory, respectively.

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Section: Testing and Debugging In A Black-box Environmentmentioning

confidence: 99%

Fault Localization Method by Partitioning Memory Using Memory Map and the Stack for Automotive ECU Software Testing

2016

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“…In this work the authors observe internal signals using the device-readback feature of certain FPGAs, which allows all registers within the FPGA to be read while the device is stopped. However, starting and stopping the circuit for each instruction will often disrupt interactions with other parts of the system, making it difficult to reproduce bugs [22].…”

Section: Related Workmentioning

confidence: 99%

Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs

Goeders

Wilton

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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High-level synthesis (HLS) for FPGA designs has received considerable attention in recent years. To make this design methodology mainstream, improved debugging technologies are essential. Ideally, a user should be able to debug their design using the original source code, without detailed knowledge of the underlying hardware, while the circuit executes in-situ. Although recent work has made progress toward this goal, existing solutions lack a full system for obtaining visibility into circuits that have been heavily optimized by the compiler. HLS compilers typically perform many optimizations, including moving variable values out of memories and into registers distributed throughout the design. Debugging such circuits typically requires either understanding the hardware and probing the appropriate RTLlevel registers, or ignoring these variables while debugging the design, neither of which is desirable.In this work we present a new signal-tracing technique, specifically designed for circuits that have been optimized by an HLS tool. We build on past work which extracts information from the HLS process to determine which signals are relevant to record each cycle. We automatically embed circuitry which dynamically selects the relevant signals, cycle-by-cycle, and records them into on-chip memories. In addition, we explore techniques to balance tracing between cycles to further improve memory efficiency. For each 100Kb of memory allocated to trace buffers, our technique can, on average, record and replay 4322 lines of source code, versus 141 lines using conventional tracing methods.

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“…It also requires only a small amount of additional debug logic in the SoC. 2 The main disadvantage of interactive debug is that because the SoC must be stopped prior to observing its state, the technique is intrusive. The captured state of a GALS SoC, therefore, is not necessarily consistent.…”

Section: Observabilitymentioning

confidence: 99%