Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?

Logic-level mapping of high-level faults

“…Is this only by chance? No, it is not; Section 6 shows that bit coverage faults are a good sample for the set of stuck-at faults [11].…”

Analysis and comparison of functional verification and ATPG for testing design reliability

“…Other works try to find a correlation between high-level functional coverage models and gate-level fault models (they try to utilise e.g. bit coverage in [6] or statement coverage in [7]). However, no clear conclusions are drawn with respect to the use of mixed, cross-layer information to improve overall test results.…”

Efficient RTL Coverage Metric for Functional Test Selection

“…VVG [12] extends the toggle metric to include propagation but requires RTL fault simulation which is expensive. Later works extend the fault model, by considering not only RTL line stuck-at faults, but also condition stuck faults [13], and additional stuck-at faults inside the blocks whose structures are unknown at RTL [14]. In this paper, we concentrate on an efficient technique that has the same order of complexity as logic simulation.…”

“…Even though it is preferable to use register-transfer-level (RTL) coverage metrics, existing RTL metrics either do not establish the correlation with gate-level fault models [6][7][8][9][10], or require expensive fault simulation [11][12][13][14]. Current approaches to functional test selection for manufacturing testing are ad-hoc and often use structural coverage metrics such as toggle coverage [15], which gives suboptimal results.…”