Functional verification methodology for microprocessors using the Genesys test-program generator

Fournier, Laurent Sébastien; Arbetman, Y.; Levinger, M.

doi:10.1145/307418.307540

Cited by 39 publications

(13 citation statements)

References 9 publications

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“…A test generator (e.g. [7,1]) produces a test program containing the results expected by the processor specification after each instruction (the expected results). These results are usually obtained using a software that can calculate the expected results after each instruction, known as a golden model.…”

Section: Ibi Backgroundmentioning

confidence: 99%

Checking architectural outputs instruction-by-instruction on acceleration platforms

Chatterjee

Koyfman

Morad

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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Simulation-based verification is an integral part of a modern microprocessor's design effort. Commonly, several checking techniques are deployed alongside the simulator to detect and localize each functional bug manifestation. Among these, a widespread technique entails comparing a microprocessor design's outputs with a golden model at the architectural granularity, instruction-by-instruction. However, due to exponential growth in design complexity, the performance of software-based simulation falls far short of achieving an acceptable level of coverage, which typically requires billions of simulation cycles. Hence, verification engineers rely on simulation acceleration platforms. Unfortunately, the intrinsic characteristics of these platforms make the adoption of the checking solutions mentioned above a challenging goal: for instance, the lockstep execution of a software checker together with the design's simulation is no longer feasible.To address this challenge we propose an innovative solution for instruction-by-instruction (IBI) checking tailored to acceleration platforms. We provide novel design techniques to decouple event tracing from checking by including specialized tracing logic and by adding a post-simulation checking phase. Note that simulation performance in acceleration platforms degrades when increasing the number of signals that are traced; hence, it is imperative to generate a compact summary of the information required for checking, collecting and tracing only a few bits of information per cycle.

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Section: Ibi Backgroundmentioning

confidence: 99%

Checking architectural outputs instruction-by-instruction on acceleration platforms

Chatterjee

Koyfman

Morad

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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“…As a result, the generated tests are used only for simulation and cannot be used on the emulator, tester or the final silicon. IBM's Genesys [8]- [10] tool is another model-based [11] testprogram generator for microprocessor verification. The tool has 3 components: a generic, architecture-independent test generator; an external specification (the model) that has a formal description of the targeted architecture; and finally a behavioral simulator for the targeted architecture.…”

Section: Related Workmentioning

confidence: 99%

“…(atom "add.32 %src = %zero, " (rand-data))) 8 (synchronize 'execute) 9 ;; schedule the producing and consuming atoms "offset" molecules apart 10 (sch-atom-group! (atom prod-op "%bypassed = %zero, " (rand-data)) 11 (atom con-op "%result = %bypassed, %src") and adopted.…”

Section: B Coding Guidelines To Facilitate Mixingmentioning

confidence: 99%

DVGen: Increasing Coverage by Automatically Combining Test Specifications

Rich¹,

Shaw²,

Govindaraju³

et al. 2006

2006 IEEE International High Level Design Validation and Test Workshop

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DVGen is a novel microprocessor test generator that allows the verification engineer to focus only on capturing test intent via minimally constrained test specifications. DVGen combines test specifications to generate tests that preserve the intent of each specification while causing the concurrent occurrence of interesting events from each specification. DVGen is very effective at uncovering multi-dimensional corner case bugs, which have historically been the bane of complex designs.

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“…Coverage tools are used side by side with random test generator in order to assess the progress of the test plans during the verification cycle. The coverage analysis allows for (1) the modification of the directives for the test generators; and (2) the targeting of areas of the design that are not covered well [6]. This process of modifying the directives for the test generator according to feedback based on coverage reports (called Coverage Directed test Generation (CDG)) is a manual and exhausting process, but essential for the completion of the verification cycle.…”

Section: Introductionmentioning

confidence: 99%

Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm

Samarah

Habibi

Tahar

et al. 2006

2006 IEEE International High Level Design Validation and Test Workshop

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Functional verification is a major challenge in the hardware design development cycle. Defining the appropriate coverage points that capture the design's functionalities is a non-trivial problem. However, the real bottleneck remains in generating the suitable testbenches that activate those coverage points adequately. In this paper, we propose an approach to enhance the coverage rate of multiple coverage points through the automatic generation of appropriate test patterns. We employ a directed random simulation, where directives are continuously updated until achieving acceptable coverage rates for all coverage points. We propose to model the solution of the test generation problem as sequences of directives or cells, each of them with specific width, height and distribution. Our approach is based on a genetic algorithm, which automatically optimizes the widths, heights and distributions of these cells over the whole input domain with the aim of enhancing the effectiveness of test generation. We illustrate the efficiency of our approach on a set of designs modeled in SystemC.

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Functional verification methodology for microprocessors using the Genesys test-program generator

Cited by 39 publications

References 9 publications

Checking architectural outputs instruction-by-instruction on acceleration platforms

Checking architectural outputs instruction-by-instruction on acceleration platforms

DVGen: Increasing Coverage by Automatically Combining Test Specifications

Automated Coverage Directed Test Generation Using a Cell-Based Genetic Algorithm

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