1997
DOI: 10.1147/rd.414.0549
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Functional verification of the CMOS S/390 Parallel Enterprise Server G4 system

Abstract: Verification of tlie S/390® Parallel EnterpriseServer G4 processor and level 2 cache (L2) chips was performed using a different approach than previously. This paper describes the methods employed by our functional verification team to demonstrate that its logical system complied with the S/390 architecture while staying within the changing cost structure and time-to-market constraints. Verification proceeded at four basic levels defined by the breadth of logic being tested. The lowest level, designer macro ver… Show more

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Cited by 16 publications
(9 citation statements)
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“…Since i390 architecture consists of zSeries instructions, VM/ESA* and z/VM* are ideal environments in which to execute such code. This provides a tremendous performance advantage over hardware simulation models that interpret each instruction cycle by cycle [4,5]. However, running i390 code on plain VM/CP is not possible, since i390 uses many additional instructions that are not provided by underlying hardware or VM/CP.…”
Section: Execution Environmentmentioning
confidence: 99%
“…Since i390 architecture consists of zSeries instructions, VM/ESA* and z/VM* are ideal environments in which to execute such code. This provides a tremendous performance advantage over hardware simulation models that interpret each instruction cycle by cycle [4,5]. However, running i390 code on plain VM/CP is not possible, since i390 uses many additional instructions that are not provided by underlying hardware or VM/CP.…”
Section: Execution Environmentmentioning
confidence: 99%
“…The new Unix(AIX) environment also prompted a more efficient implementation of all the algorithms for model creation. The new simulator was named "Texsim" [7], [8]. Texsim gained its efficiency from a Boolean network database optimized for mapping HDL descriptions to machine instructions.…”
Section: A Verificationmentioning
confidence: 99%
“…For example, while a 601 PowerPC (1 million transistors) model takes less than 2 min to build from HDL source and shows a simulation throughput of 350 cycles/s, it is possible to build an eight-way Power3 (16M transistors/processor, or 128M transistors/system) model in less than 15 min with a resulting throughput of 10 cycles/s (all numbers based on an RS/6000 595). All of IBM's microprocessor systems have been simulated with Texsim since 1992 [8].…”
Section: A Verificationmentioning
confidence: 99%
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