Functional verification of the IBM POWER7 microprocessor and POWER7 multiprocessor systems

Schubert, Klaus-Dieter; Roesner, Wolfgang; Ludden, John M.; Jackson, Jonathan R.; Buchert, Jacob; Paruthi, Viresh; Behm, Michael; Ziv, Avi; Schumann, John; Meissner, Charles; Koesters, Johannes; Hsu, James; Brock, Bishop

doi:10.1147/jrd.2011.2117370

Cited by 22 publications

(9 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As in previous POWER generations [2], the memory subsystem continues to be an area of much complexity and associated verification challenges. In Power systems built with POWER8 technology, the functional split between the processor chip and the memory buffer chip evolved from previous projects, moving some logic, including a new cache for performance improvements, towards the buffer chip.…”

Section: Memory Stack Formal Verificationmentioning

confidence: 99%

See 1 more Smart Citation

Solutions to IBM POWER8 verification challenges

Schubert

Ludden

Ayub³

et al. 2015

IBM J. Res. & Dev.

Self Cite

View full text Add to dashboard Cite

This paper describes methods and techniques used to verify the POWER8i microprocessor. The base concepts for the functional verification are those that have been already used in POWER7 A processor verification. However, the POWER8 design point provided multiple new challenges that required innovative solutions. With approximately three times the number of transistors available, compared to the POWER7 processor chip, functionality was added by putting additional enhanced cores on-chip and by developing new features that intrinsically require more software interaction. The examples given in this paper demonstrate how new tools and the continuous improvement of existing methods addressed these verification challenges.

show abstract

Section: Memory Stack Formal Verificationmentioning

confidence: 99%

“…The verification of the POWER8 design started with the POWER7* environment including all the verification improvements described in [2]. As in prior projects [3], an hierarchical verification approach was used, starting with the unit-level (e.g., the floating point unit (FPU), the L2 cache unit, etc.…”

Section: Introductionmentioning

confidence: 99%

Solutions to IBM POWER8 verification challenges

Schubert

Ludden

Ayub³

et al. 2015

IBM J. Res. & Dev.

Self Cite

View full text Add to dashboard Cite

show abstract

“…An overview of the post-silicon methodology used in the POWER8 bring-up lab is described in [3]. Another key aspect to this methodology is the usage of the Awan simulation acceleration platforms [1] to prepare exercisers for the lab. Two of the exercisers used in the POWER8 lab are described in more detail in [21,22].…”

Section: Related Workmentioning

confidence: 99%

“…We employ an advanced methodology and a suite of techniques in a variety of simulation environments for verifying the design of our POWER* processors [1,2]. Due to the trends described by Moore's Law, the sooner a computer ships, the more competitive it will be.…”

Section: Introductionmentioning

confidence: 99%

Debugging post-silicon fails in the IBM POWER8 bring-up lab

Dusanapudi¹,

Fields²,

Floyd³

et al. 2015

IBM J. Res. & Dev.

View full text Add to dashboard Cite

Debugging post-silicon fails continues to be a difficult problem that is becoming even more challenging as chips integrate more functionality and implement increasingly complicated functions. Additionally, the complexity of hardware systems, coupled with the difficulty in observing the state of the system that led to the failure, make the debugging effort a unique challenge. In this paper, we review the techniques and mechanisms used to facilitate effective debugging in the POWER8i processor post-silicon validation phase. We further describe several functional bugs and describe the debugging process that drove the identification of their root cause.

show abstract

“…IBM has invested heavily on verification technology for years. They have developed a series of independent tools which include cycle-accurate software simulation MESA, hardware accelerator AWAN, formal tools SIxthSense and RuleBase [17,18]. A hybrid RAIM (redundant array of independent memory) method was used for the IBM zEnterprise processor verification which contained 80 configurable cores.…”

Section: Related Workmentioning

confidence: 99%

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

Pan¹,

Tang²,

Guodong³

et al. 2014

TOCSJ

View full text Add to dashboard Cite

Abstract:Functional verification has become a major challenge in the chip design area. To improve the efficiency of verification, it is necessary to choose appropriate verification method and tools. An important aspect of functional verification is RTL verification, simulation-based verification is main method in RTL verification. Based on FT-8 multicore processor, we developed a configurable test stimulus acceleration method, loading the test stimulus into memory and L2 cache to speed up the processor instructions fetch, which can shorten simulation cycle and simulation time, reduce the verification cost and guaranteed the correctness of design.

show abstract

Functional verification of the IBM POWER7 microprocessor and POWER7 multiprocessor systems

Cited by 22 publications

References 12 publications

Solutions to IBM POWER8 verification challenges

Solutions to IBM POWER8 verification challenges

Debugging post-silicon fails in the IBM POWER8 bring-up lab

Configurable Verification Stimulus Acceleration Method Based on Multicore Processor

Contact Info

Product

Resources

About