Hardware/software (HW/SW) co-verification can considerably shorten the time required for system integration and bring-up. But coverification is limited by the simulation speed achievable whenever hardware models are required to verify hardware and software interactions. Although the use of a generalpurpose hardware accelerator as an extremely fast simulator resolves performance aspects, it generates a new set of handling, efficiency, and serviceability demands. This paper describes a means for addressing those demands through the use of one of the largest hyper-acceleration systems created thus far, and describes many new associated features that have been implemented in operating software.

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The post-silicon validation phase in a processor's design life cycle is geared towards finding all remaining bugs in the system. It is, in fact, our last opportunity to find functional and electrical bugs in the design before shipping it to customers.In this paper, we provide a high-level overview of the methodology and technologies put into use as part of the POWER8 post-silicon functional validation phase. We describe the results and list the primary factors that contributed to this highly successful bring-up.

This paper describes methods and techniques used to verify the POWER8i microprocessor. The base concepts for the functional verification are those that have been already used in POWER7 A processor verification. However, the POWER8 design point provided multiple new challenges that required innovative solutions. With approximately three times the number of transistors available, compared to the POWER7 processor chip, functionality was added by putting additional enhanced cores on-chip and by developing new features that intrinsically require more software interaction. The examples given in this paper demonstrate how new tools and the continuous improvement of existing methods addressed these verification challenges.