Hardware/software (HW/SW) co-verification can considerably shorten the time required for system integration and bring-up. But coverification is limited by the simulation speed achievable whenever hardware models are required to verify hardware and software interactions. Although the use of a generalpurpose hardware accelerator as an extremely fast simulator resolves performance aspects, it generates a new set of handling, efficiency, and serviceability demands. This paper describes a means for addressing those demands through the use of one of the largest hyper-acceleration systems created thus far, and describes many new associated features that have been implemented in operating software.

In the development of a large, complex computer system, the verification of its microcode by simulation can significantly decrease the time required for the integration, "bring up," and testing of the system. However, creating a process that integrates and aligns the smaller verification tasks to form a coordinated, seamless, and comprehensive system verification plan requires considerable effort. In this paper we present a brief summary of previous verification processes and describe a process, virtual power-on (VPO), which encompasses both hardware and software verification. We then compare the results achieved with that process with those achieved using previous processes. The VPO process was initially applied to the IBM eServer z900, resulting in a significant reduction in the time required for its development.

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With the IBM eServer z900, simulation methods and tools for verification of code that is to be embedded in the memory of the system (firmware) were introduced. Since that time, firmware developers have simulated their code prior to the availability of new system hardware components, thereby reducing the time required to bring a large computer system to market. With the z990 system, code simulation efficiency has been improved. The simulation coverage for host and service firmware has been increased from approximately 60% in the z900 to 85% in the z990 by introducing new concepts and extensions. For the first time, the central electronic complex (CEC) firmware simulator, CECSIM, has been enabled to run code in a logical partition (LPAR). This was a prerequisite for code verification of the intra-CEC connectivity, HiperSockets. For verification of HiperSockets, a Linux operating system is loaded into an LPAR. Code verification is accomplished more easily, more effectively, and with better coverage using Linux debugging features because of the ease of performing functional tests with Linux. Another major improvement was the connection of the channel code simulator for the networking I/O adapter OSA-Express to the CECSIM environment to provide a comprehensive verification that covers the entire path of firmware interaction between the CEC and the I/O channels. For the simulation of card control code, a combined software and hardware verification approach was introduced. The overall functionality was verified with a system simulation model, and the base hardware accesses were verified by attaching real hardware. In addition, the cage controller code was integrated into the simulation environment. As a result, the firmware interfaces between the support element (SE) and the cage controller as well as between the cage controller and the hardware have been tested.

1Multiple and unpredictable numbers of actions are often required to achieve a goal. In order to 2 organize behavior and allocate effort so that optimal behavioral policies can be selected, it is 3 necessary to continually monitor ongoing actions. Real-time processing of information related to 4 actions and outcomes is typically assigned to the prefrontal cortex and basal ganglia, but also 5 depends on midbrain regions, especially the ventral tegmental area (VTA). We were interested 6 in how individual VTA neurons, as well as networks within the VTA, encode salient events 7 when an unpredictable number of serial actions are required to obtain a reward. We recorded 8 from ensembles of putative dopamine and non-dopamine neurons in the VTA as animals 9 performed multiple cued trials in a recording session where, in each trial, serial actions were 10 randomly rewarded. While averaging population activity did not reveal a response pattern, we 11 observed that different neurons selectively tuned to low, medium, or high numbered actions in a 12 trial. This preferential tuning of putative dopamine and non-dopamine VTA neurons to different 13 subsets of actions in a trial allowed information about binned action number to be decoded from 14 the ensemble activity. At the network level, tuning curve similarity was positively associated 15 with action-evoked noise correlations, suggesting that action number selectivity reflects 16 functional connectivity within these networks. Analysis of phasic responses to cue and reward 17 revealed that the requirement to execute multiple and uncertain numbers of actions weakens both 18 cue-evoked responses and cue-reward response correlation. The functional connectivity and 19 ensemble coding scheme that we observe here may allow VTA neurons to cooperatively provide 20 a real-time account of ongoing behavior. These computations may be critical to cognitive and 21 motivational functions that have long been associated with VTA dopamine neurons. 22