In this paper, focuses on the design of Low Noise Amplifier circuitry in the frequency band L. This circuit is designed using the 0.18 nm CMOS transistor technology, which consists of two transistor Stage. The purpose of this research is to improve the cost of: Increase Gain -Increase circuit linearization -Create an integrative matching network for system stability. The application of this circuit can be used in wireless and GPS systems. The CMOS LNA exhibits a gain greater than 23 dB from 1.1 to 2.0 GHz, and a noise figure of 2.7 to 3.3 dB from 1.2 to 2.4 GHz. At 1.575 GHz, the 1 -dB compression point (P1dB) is 1.73 dBm, with an input third-order intercept point (IIP3) of -3.98 dBm. This circuit is designed using ADS software.
Keywords:Gain; Noise Figure
1-IntroductionBuilt-in Global Positioning System (GPS) capability is increasingly becoming a standard feature for cellular handset and other low-cost embedded applications. The requirements for these systems provide a strong motivation for developing highly integrated and low-cost GPS receivers. Low-noise amplifiers (LNAs) in GPS receivers are often the most challenging block to implement, given the difficulty of simultaneously achieving sufficient gain, low noise figure, and low power consumption. Typically, GPS receivers operate in the L-band frequency range (1575.42 MHz (L1), 1227.60 MHz (L2), 1381.05 MHz (L3) and 1176.45 MHz (L5)). Designing a monolithic LNA at L-band poses significant challenges due to the large size of the passive components, making it difficult to implement the LNA with its requisite matching networks on-die. Complementary Metal-Oxide-Semiconductor (CMOS) [1] are attractive for analog, mixed-signal and RF applications because they exhibit very low noise figure and very high power gain, at modest power dissipation levels, which can be leveraged to improve the sensitivity of receiver front-ends. CMOS technology utilizes band gap engineering to improve transistor performance, and at present peak cutoff frequency (fT) and peak maximum oscillation frequency (fmax) greater than 300 GHz have been achieved at modest lithographic feature size (0.18 nm), while maintaining compatibility with the traditional CMOS processes In this paper, we present a high gain, L-band CMOS LNA with fully-integrated on-chip matching networks. At 1.575 GHz, the LNA achieves a gain of 26 dB, a NF of 3.2 dB, while dissipating 17.89 mW of dc power.Communication systems have been improving a lot in the last decades [1]. An important factor determining their improvement is on RF front end circuits [4,6,8,9]. RF front-end components with high linearity and flat gain performance as well as high efficiency and low thermal dissipation loss are highly necessary [2,3,5,7]. In case of satellite telecommunication, signal transmission travelling thousands of miles from the ground station-to-satellite and satellite-to-receiving fixed and mobile stations demands RF front-end transistors meeting stringent requirements. Specifications, including the low noise amplifier of rec...